NT68F62 Datasheet, PDF (43/57 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K Flash MTP Type)

NT68F62
15.4 DDC2B+ Master Mode Bus Interface
Most of the DDC manipulation is the same as SLAVE mode
except the SCL clock generation. In the MASTER mode,
the control of the SCL clock source belongs to NT68F62.
Users must set the calling address and transmission
direction in advance. Access the MODE & MRW bits to
control the transmission flow of DDC2B+ master mode
communication.
Start condition: After user clears the ENDDC & MODE
bits, the system will generate a 'START' condition on the
SCL & SDA lines and wait for the user to put the calling
address into the TXDAT buffer and send it to SDA line. The
frequency of SCL is dependant on the baud-rate setting
value (DDCBR0 - DDCBR2) in the register CH0CLK. The
data transmission direction will be dependant on the MRW
bit and the LSB of the calling address, '1' for read operation
and '0' for write operation.
Calling address: The calling address is 8 bits long. It should
be put in the CH0TXDAT. The setting of the LSB bit in this
TXDAT buffer should be the same as the MRW bit.
STOP condition: There are several cases in which the
system will send out a 'STOP' condition on the SCL & SDA
lines. First, in the 'READ' operation, if the user sets the
TXACK bit to '1', the system will send out the 'NAK'
condition on the bus after receiving one byte of data and
will then send out the 'STOP' condition automatically later.
Second, in the 'START' condition and after the sending out
a calling address, if no slave has responded to an 'ACK'
signal, the master will send out the 'STOP' condition
automatically. Third, if the user sets the MODE bit to '1',
the system will generate a 'STOP' condition after the
current byte transmission is done. Notice that if the slave
device did not release the SCL and SDA line, the system
can not send out the 'STOP' condition.
After the 'STOP' condition, the master will release the SCL
& SDA lines and return to SLAVE mode.
The INTTX0 & INTRX0 interrupt: After NT68F62 completes
one byte transmission or receiving of data, it will generate
INTTX0 (WRITE mode) & INTRX0 (READ mode) interrupts.
Users can control the flow of DDC2B transmission at these
interrupts.
The INTRX0 on the read mode: NT68F62 reads data from
an external slave device. When users detect an INTRX0
interrupt, it means that one byte data has been received
and the user can read out by accessing CH0RXDAT control
register. At the same time, if the user sent an 'ACK' signal
beforehand, the shift register will send out an 'ACK' bit (low
voltage) and continue to receive the next byte of data. If
both the shift register and the CH0RXDAT register are full
and the user still does not load data from the CH0RXDAT
register, the SCL will be held LOW and will wait for
NT68F62. After the user has received one byte of data
from the CH0RXDAT register, the SCL will be released for
generation of SCL transmission clock. An external device
can continue sending the next byte of data to NT68F62.
Refer to Figure 15.7 for the timing diagram. The user must
respond to a NAK signal in advance to stop the
transmission. Before the last two bytes of data are
received, the user should respond with a 'NAK' signal.
Then, the system will send out a 'NAK' bit after receiving
the last byte of data and enact the 'STOP' condition to
notify the slave that current transmission is terminated.
The INTTX0 on the WRITE mode: The external device
reads data from NT68F62. During an INTTX0 interrupt, the
system will load new data (that the user has already put
into the internal shift register) from the CH0TXDAT register
and continue sending out this new data. After this new
loading data has been shifted out by every SCL clock, the
system will request the user to put the next byte of data into
the CH0TXDAT register.
If both of the shift register and the CH0TXDAT register are
empty and the user still cannot load data into the
CH0TXDAT register, the NT68F62 system will let SCL pin
keep ‘LOW’ and wait the another new data after receiving
the acknowledgment bit from external device.
If SCL is held low by the system, and the user has put one
new byte of data into the CH0TXDAT register, the SCL will
be released for generation of SCL transmission clock. At
this time, the system will load this byte of data into the shift
register and generate an INTTX0 interrupt again to remind
the user to put the next byte into the CH0TXDAT register.
Refer to Figure 15.8 for the timing diagram.
Repeat start condition: If the user clears the RSTART bit
to '0' in the ' WRITE' operation, the system will send out a
'Repeat Start'. Notice that if the slave device does not
release the SCL and SDA lines, the system can not send
out a 'REPEAT START condition.
SCL baud rate selection: There are three Baud Rate bits for
users to select one of eight clock rates on the SCL line.
After a system reset, the default value of these Baud Rate
bits (DDC2BR0-2) are '111'.
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