NT68F62 Datasheet, PDF (26/57 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K Flash MTP Type)

NT68F62
13.1. V & H Counter Register: VCNTL/H, HCNTL/H
Vsync counter: VCNTL/H, the 14-bit READ ONLY register, contains information on the Vsync frequency. An internal counter
counts the numbers of 8us pulses between two VSYNC pulses. When the next VSYNC signal is recognized, the counter is
stopped and the VCNTH/L register latches the counter value. Then the counter counts from zero again for evaluating the
next VSYNC time interval. The counted data can be converted to the time duration between two successive Vsync pulses. If
there is no VSYNC signal , the counter will overflow and set the VCNTOV bit (in the VCNTH register) to HIGH. Once the
VCNTOV is set to HIGH, it stays in the HIGH state until '1' is written to it (CLRVOV bit).
Hsync counter: If the ENHSEL bit is set to HIGH, the internal counter counts the Hsync pulses between two Vsync pulses.
The HCNTL/H control registers contain the numbers of Hsync pulse between two Vsync pulses. These data can determine if
the Hsync frequency is valid or not to determine the accurate video mode.
The system supports two other options of the time interval for the user to count the frequency of Hsync pulses. If users clear
the ENHSEL and set the HSEL bits properly, this internal counter counts the Hsync pulses during a system defined time
interval. The time interval is defined below:
ENHSEL
1
0
0
HSEL
-
0
1
Hsync Freq
Disabled
16.384 ms
32.768 ms
Note
After system reset or users disabling
After system reset, this interval will be disabled and the content of ENHSEL & HSEL0 bits will be '1'. When this function is
disabled, the HCNTL/H counter works on the VSYNC pulse. It is invalid to write '00' to them.
Latching the hsync counter: The counted value will be latched by the HCNTH/L register pairs that are updated by the Vsync
pulse or by the system defined time interval. (Refer to the Figure 13.4 for the operation of the HCNTL/H counter.) If the
counter overflows, the HCNTOV bit (in the HCNTH register) will be set to HIGH. Once the HCNTOV is set to HIGH, it keeps
in the HIGH state until '1' is written to it (CLRHOV bit). When setting this CLRHOV bit, the HCNT counter will not be reset to
zero.
VSYNCI
Latch HCNT register
Reset H sync. counter
Start pulse counting
Latch HCNT register
Reset H sync. counter
Start pulse counting
HSYNCI
16.384ms/32.768ms
(Setting HSEL0/1 bits)
HSYNCI
Figure 13.4. Hsync Counter Operation
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