NT68F62 Datasheet, PDF (21/57 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K Flash MTP Type)

NT68F62
12. I/O PORTs
The NT68F62 has 25 pins dedicated to input and output.
These pins are grouped into 4 ports.
12.1. PORT0: P00 - P07
PORT0 is an 8-bit bi-directional CMOS I/O port with PMOS
as internal pull-up (Figure 12.1). Each pin of PORT0 may
be bit programmed as an input or output port without
software controlling the data direction register. When Port0
works as an output, the data to be output are latched to the
port data register and output to the pin. PORT0 pins that
have '1's written to them are pulled HIGH by the internal
PMOS pull-ups. In this state they can be used as inputs
and then the input signals can be read. This port output is
high after reset.
P00 - P05 are shared with DAC7 - DAC12 respectively. If
ENDK7 - ENDK12 is set to LOW in the ENDAC register,
P00 - P05 will act as DAC7 - DAC12 respectively (Figure
12.2). After the chip is reset, ENDK7 - ENDK12 will be in
the HIGH state and P00 - P05s will act as I/O ports.
P06 、 P07 are shared with VSYNCO & HSYNCO
respectively. If ENHOUT、 ENVOUT is set to LOW in the
HVCON register, P06 、 P07 will act as VSYNCO &
HSYNCO respectively (Figure 12.3). After the chip is reset,
ENHOUT & ENVOUT will be in the HIGH state and
P06、P07 will act as I/O pins.
Addr.
$0000
$0007
Register
PT0
HV CON
$000F ENDAC
INIT
Bit7
FFH
P07
FFH
―
Bit6
Bit5
Bit4
Bit3
Bit2
P06
P05
P04
P03
P02
―
HSYNCI VSYNCI HPOLI
VPOLI
FFH ENHOUT ENVOUT
―
―
―
―
FFH
―
―
ENDK12 ENDK11 ENDK10 ENDK9
Bit1
P01
HPOLO
HPOLO
ENDK8
Bit0
R/W
P00
RW
VPOLO
R
VPOLO W
ENDK7 W
VDD
PWM
Data In
PWM
Output
Data Out
I/O
Figure 12.2. PWM Output Structure
VDD
Data In
Figure 12.1. I/O Structure
O/P
Data Out
Figure 12.3. Output Structure
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