NT68F62 Datasheet, PDF (41/57 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K Flash MTP Type)

NT68F62
Data transfer and wait: The data on the SDA line must be
stable during the HIGH period of the clock on the SCL line.
The HIGH and LOW state of the SDA line can only change
when the clock signal on the SCL line is LOW. Each byte of
data is eight bits long and one clock pulse for one bit of
data transfer. Data is transferred with the most significant
bit (MSB) first. In the wired-AND connection, any slower
device can hold the SCL line LOW to force the faster
device into a waiting state. Data transmission will be
suspended until the slower device is ready for the next byte
transfer by releasing the SCL line.
Acknowledge: The acknowledgment will be generated at
the ninth clock by whomever is receiving data. In the
WRITE MODE, the NT68F62 system must respond to this
acknowledgment. Users should clear the TXACK bit in the
CH0CON to open the ‘ACK’ function. After receiving one
byte of data from the external device, NT68F62 will
automatically send this acknowledgment bit.
In the READ mode, an external device must respond to the
acknowledgment bit after every byte of data is sent out.
The system will set the INTNAK bit when the external
device does not send out the '0' acknowledgment bit.
Furthermore, the user can open this interrupt source by
clearing the INTNAK bit in the IEIRQ0 register.
The INTTX0 & INTRX0 interrupt: After NT68F62 completes
one byte transmission or receiving, it will generate INTTX0
(READ mode) & INTRX0 (WRITE mode) interrupts. These
interrupts are generated at the falling edge of the ninth
clock. Users can control the flow of DDC2B transmissions
at these interrupts.
The INTRX0 on the WRITE mode: NT68F62 reads data
from the external master device. When users detect an
INTRX0 interrupt, it means that one byte of data has been
received and the user can read out by accessing the
CH0RXDAT control register. At the same time, if the user
responded to an 'ACK' signal beforehand, the shift register
will send out this 'ACK' bit (low voltage) and continue to
receive the next byte data. If both of the shift register and
the CH0RXDAT register are full and the user still does not
load data from the CH0RXDAT register, the NT68F62
system will let the SCL pin keep ‘LOW’ and will wait for
user to retrieve this collected data. After the user obtains
one byte of data from the CH0RXDAT register, the SCL will
be released for generation of the SCL transmission clock.
At this time , the external device can continue sending the
next byte of data to NT68F62. The timing diagram refers to
Figure 15.3. The user must respond with a NAK signal
beforehand to stop the transmission.
The INTTX0 on the READ mode: An external device can
read data from NT68F62. During INTTX0 interrupt, the
system will load new data from the CH0TXDAT register
which the user has earlier put into this internal shift register.
Then , the system will begin to send out this new data
continually . After this newly loaded data had been shifted
out by every SCL clock, the system will request the user to
put the next byte of data into the CH0TXDAT register by
the INTTX0 interrrupt.
If both of the shift register and the CH0TXDAT register are
empty and the user still cannot load data into the
CH0TXDAT register, the NT68F62 system will let SCL pin
keep ‘LOW’ and wait the another new data after receiving
the acknowledgment bit from external device.
When SCL is held low by the system and after the user had
put one new byte of data into the CH0TXDAT register, the
SCL will be released for generation of the SCL
transmission clock. At this time, the system will load this
byte of data into the shift register and generate an INTTX0
interrupt again to remind the user to putt the next byte into
the CH0TXDAT register. For the timing diagram refer to
Figure 15.4.
After every one byte of data transfer, the system will
monitor if the external master device has sent out the
acknowledgment bit or not. If not, the system will set the
INTNAK bit (the acknowledgment is LOW signal). Users
will get an INTNAK interrupt if the INTNAK has been
enabled as a interrupt source.
STOP condition: When SCL & SDA lines have been
released (held on 'high' state), DDC2B data transfer is
always terminated by a STOP condition generated by an
external device. A STOP signal is defined as a LOW to
HIGH transition of SDA while SCL is at HIGH state. When
there is a STOP condition, NT68F62 will set the 'STOP' bit
& INTSTOP bit to '1' and the user can poll this status bit or
open a INTSTOP interrupt to control the DDC2B
transmission at any time. This bit will stay as '1' until the
user clears it by writing '1' to this bit. Notice: The SCL and
SDA lines must conform to IIC bus specifications. For the
software flowchart please refer to Figure 15.6. Please refer
to the standard IIC bus specification for details.
Change to DDC1 mode: After an external device terminates
DDC2 transmission by sending a STOP condition, users
can set MD1/ 2 to '1' for changing to DDC1 mode. On the
other hand, when the SCL line has been released (pulled-
up), the user can force NT68F62 to DDC1 mode
communication at any time.
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