NT68F62 Datasheet, PDF (17/57 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K Flash MTP Type)

NT68F62
10. Watch-Dog Timer (WDT)
The NT68F62 implements a watch-dog timer reset to avoid
system stop or malfunction. The clock of the WDT is taken
from the on-chip RC oscillator, which does not require any
external components. Thus, the WDT will run, even if the
clock on the OSCI/OSCO pins of the device has been
stopped. The WDT time interval is about 0.5 second. The
as; LDA #$55
STA $0020
Addr. Register
INIT
Bit7
Bit6
Bit5
$0020 CLR WDT
-
0
1
0
11. Interrupt Controller
The system provides two kinds of interrupt sources: NMI &
IRQ. The NMI cannot be masked if user enabled this NMI
interrupt. Users will execute the NMI interrupt vector any
time that sources are activated. The IRQ interrupts can be
masked by executing a CLI instruction or by setting the
interrupt mask flag directly in the µC status register. In the
process of an IRQ interrupt, if the interrupt mask flag is not
set, the µC will begin an interrupt sequence. The program
counter and processor status register will be stored in the
stack. The µC will then set the interrupt mask flag high so
that no further interrupts may occur. At the end of this
cycle, the program counter will be loaded from addresses
$FFFE & $FFFF, thus transferring program control to the
memory vector located at these addresses. For NMI
interrupt, µC will transfer execution sequence to the
memory vector located at addresses $FFFA & $FFFB.
WDT must be cleared within every 0.5 second when the
software is in normal sequence, otherwise the WDT will
overflow and cause a reset. The WDT is cleared and
enabled after the system is reset, and can not be disabled
by the software. Users can clear the WDT by writing 55H to
the CLRWDT register ($0020).
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
0
1
W
When manipulating various interrupt sources, NT68F62
divides them into two groups for accessing them easily.
One is the NMI group and the other is the IRQ group.
- The NMI group includes INTE0, INTMUTE.
- The IRQ group includes the subgroup of IRQ0,
IRQ1,RQ2:
IRQ0: DDC1/2B+ Channel 0 interrupt sources; It
includes INTS0, INTA0, INTTX0, INTRX0,
INTNAK0 and INTSTOP0 interrupts.
IRQ1: DDC1/2B+ Channel 1 interrupt sources; It
includes INTS0, INTA1, INTTX1, INTRX1,
INTNAK1 and INTSTOP1.
IRQ2: It includes INTADC, INTV, INTE1 and INTMR
interrupt sources.
Below are the interrupt sources.
Nonmaskable Interrupt Group:
Interrupt
INTE0 INT
Meaning
External 0 INT
INTMUTE
Auto Mute
Maskable Interrupt Group:
Interrupt
INTADC
Meaning
A/D Conversion
Done
INTV INT
INTE1 INT
Vsync INT
External 1 INT
INTMR INT
Timer INT
Action
It will be activated by the rising or falling edge of the external interrupt pulse.
The triggered edge can be selected by EDGE0 bit.
It will be activated when the mute condition occurs (Hsync frequency change).
Please refer the synprocessor section for a more detailed explanation.
Action
User activates the ADC by clearing the CSTART bit. When the AD
conversion is done, this bit will be set.
It will be activated by the rising edge of every vsync pulse.
It will be activated by the rising or falling edge of the external interrupt pulse.
The triggered edge can be selected by EDGE1 bit.
It will be activated by the rising edge of every ??? when the Base Timer
counter overflows and counting from $FF to $00.
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