NT68F62 Datasheet, PDF (34/57 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K Flash MTP Type)

NT68F62
15. IIC Bus Interface: DDC1 & DDC2B Slave Mode
Interface: IIC bus interface is a two-wire, bi-directional
serial bus which provides a simple, efficient way for data
communication between devices, and minimizes the cost of
connecting among various peripheral devices. NT68F62
provides two IIC channels. Both of them are shared with I/O
pins and their structures are open drain. When the system
is reset, these channels are originally of general I/O pin
structure. All of these IIC bus functions will be activated
only after their ENDDC bits are cleared to '0' (CH0/1CON
registers).
DDC1 & DDC2B+ function: Two modes of operation have
been implemented in the NT68F62, uni-directional mode
(DDC1 mode) and bi-directional mode (DDC2B+ mode).
These channels will be activated as DDC1 function initially
when users enable the DDC function. These channels will
switch automatically to DDC2B+ function from DDC1
function when a low pulse greater than 500ns is detected
on the SCL line. Users can start a master communication
directly from the DDC1 communication by clearing the
MODE bit in the CH0/1CLK control register.
The channels can return to DDC1 function when users set
the MD1/ 2 bit to '1' in the CH0/1CON registers.
15.1. DDC1 bus interface
Vsync input and SDA pin: In DDC1 function, the Vsync pin
is used as an input clock pin and the SDA pin is used as a
data output pin. This function comprises two data buffers:
one is the preloading data buffer for putting one byte data
in advance by the user (CH0/1TXDAT), and the other is the
shift register for shifting out one bit data to the SDA line,
which users can not access directly. These two data buffers
cooperate properly. For the timing diagram please refer to
Figure 15.1. After the system resets, the IIC bus interface is
in DDC1 mode.
Data transfer: At first, the user must put one byte of
transmitted data into the CH0/1TXDAT register in advance,
and activate the IIC bus by setting the ENDDC bit to '0'.
Then open the INTTX0/1 interrupt source by setting
INTTX0/1 to '1' in the IEIRQ0/1 registers. On the first 9
rising edges of Vsync, the system will shift out invalid bits in
the shift register to the SDA pin to empty the shift register.
When the shift register is empty and on the next rising edge
of Vsync, it will load data from the CH0/1TXDAT registers
to the internal shift register. At the same time, the NT68F62
will shift out the MSB bit and generate an INTTX0/1
interrupt to remind the user to put the next byte data into
the CH0/1TXDAT register. After eight rising clocks, there
will have been eight bits shifted out in proper order and shift
register will become empty again. At the ninth rising clock,
it will shift the ninth bit (null bit '1') out to the SDA. And on
the next rising edge of Vsync clock, the system will
generate an INTTX0/1 interrupt again. In the same way, the
NT68F62 will load new data from the CH0/1TXDAT
registers to the internal shift register and shift out one bit
right away. Beware: the user should put one new data into
the CH0/1TXDAT registers before the shift register is empty
(the next INTTX0/1 interrupt). If not, the hardware will
transmit the last byte of data repeatedly.
Vsync clock: Only in the separate SYNC mode can the
Vsync pulse be used as a data transfer clock and its
frequency can be up to 25KHz maximum. In composite
Vsync mode, NT68F62 can not transmit any data to the
SDA pin, regardless of whether the Vsync can be extracted
from the composite Hsync signal.
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