NT68F62 Datasheet, PDF (19/57 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K Flash MTP Type)

NT68F62
Enabling Interrupts: The system will disable all of these
interrupts after reset. Users can enable each of the
interrupts by setting the interrupt enable bits at the IENMI,
IEIRQ0 ~ IEIRQ2 control registers. For example, if users
want to enable the external interrupt 0 (INTE0), write '1' to
the INTE0 bit in the IENMI control register. At the INTE0
pin, whenever NT68F62 detects an interrupt message, it
will generate an interrupt sequence to fetch the NMI vector.
Because these IEX control registers can be read, users can
read back what interrupts he has activated. At polling
sequence, users need not poll those unactivated interrupts.
Requesting Interrupts be set : No matter whether the user
has set the interrupt enable bits or not, if the interrupt
triggered condition is matched, the system will set the
correspondent bits in the IRQ0 ~ IRQ3 control registers or
in the NMIPOLL control register (INTE0 & INTMUTE bits).
For example, if at the VSYNCI pin, the system detects a
pulse occurring, the system will set the INTV bit in the IRQ2
control register.
Interrupt Groups: The system divides the IRQ interrupt
sources into several groups, ex IRQ0, IRQ1, and IRQ2. In
each of these groups, if its membership in one of the
interrupt groups has been activated, its group bit in the
IRQPOLL control register will be set. For example, if the
INTS0 of the first DDC1/2B+ channel is activated, the
INTS0 bit in the IRQ0 control register will be set and the
IRQ0 bit in the IRQPOLL control register will also be set.
Notice that the IRQ0 bit in the IRQPOLL control register will
be cleared by the system when all of its interrupt sources,
INTS0, INTA0, INTTX0, INTRX0, INTNAK0 and INTSTOP0
have been cleared by the user or the system. The NMI
group follows the same procedure as the IRQ groups.
Polling Interrupts: When an NMI interrupt occurs, during the
NMI interrupt service routine, users must poll the INTE0 &
INTMUTE bit in the NMIPOLL control register to confirm the
NMI interrupt source. The polling sequence decides the
priority of the NMI interrupt acceptance. When an IRQ
interrupt occurrs, during the IRQ interrupt service routine,
users must poll the IRQ0 – IRQ2 in the IRQPOLL control
register to confirm the IRQ interrupt source. In the same
way, the polling sequence decides the priority of the IRQ
interrupt acceptance. When deciding the IRQ source, users
can further confirm the real interrupt source by polling the
Correspondent IRQX control register ($001C - $001E).
Clearing the Interrupt Request bit: When an interrupt
occurrs, the CPU will jump to the address defined by the
interrupt vector to execute the interrupt service routine.
Users can check which one of the interrupt sources is
activated and operating a task. Upon entering the interrupt
service routine, the request bit that caused the interrupt
must be cleared by the user before finishing the service
routine and returning to the normal instruction sequence. If
users forget to clear this request bit, after returning to the
main program, it will interrupt CPU again because the
request bit remains activated. Simply, users just need to
write '1' to the polling bits in the NMIPOLL & IRQX registers
($0016 & $001C - $001E) to clear those completed
interrupt sources.
Selecting interrupt trigger edge: INTVR, INTE0R & INTE1R
interrupt sources are the edge triggered type of interrupts.
The system allows the selection of rising or falling edge
triggers to be used under the user’s control. After reset, the
rising edge triggers are provided and the content is 'FF' in
the TRIGGER control register ($001F). The user just clears
the control bits in this TRIGGER register and switches
these interrupts to be falling edge triggered.
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