NT68F62 Datasheet, PDF (36/57 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K Flash MTP Type)

NT68F62
ENDDC
(in CH0CON register)
Vsync Pulse
INTV
Load data in the CH0TXDAT
register to shift register
12 3 4
●●●
●●●
912 34 5 67 8 9 1 2
●●●
●●●
●●●
INTTX
User can load next byte data
to CH0TXDAT register
●●●
SDA
Invalid data ● ● ● 8
7
6
5
1 ● ● ● ^Null 8
7
6
Bit
5 4 3 2 1 ^Null 8
Bit
7^{● ● ●}
Shift
register
8
7
MSB
6 5 43 2 1
First Byte Data
LSB
Second Byte Data
Figure 15.1. DDC1 Mode Timing Diagram
15.2. DDC2B + Slave & Master Mode Bus Interface
The built-in DDC2B+ IIC bus Interface features are as follows:
SLAVE mode (NT68F62 is addressed by a master that
drives SCL signal)
- MASTER mode (NT68F62 addresses external
devices and sends out the SCL clock)
- Compatible with IIC bus standard
- One default $A0 slave address ( can be disabled ) and
one user programmable address
- Automatic wait state insertion
- Interrupt generation for status control
- Detection of START and STOP signals
The DDC2B+ will be activated as SLAVE mode initially.
Users can switch to MASTER mode by clearing the MODE
bit under either of these conditions listed as follows:
1. After entering into DDC1 function and clearing this bit,
the system will be changed from DDC1 to DDC2B+
MASTER mode operation.
2. After entering into DDC2B+ slave mode function and
clearing this bit, the system will be changed from slave
mode into master mode operation.
During clearing of the MODE bit, the system will send out a
'START' condition and wait for the user to put the calling
address into the CH0/1TXDAT control register. Notice: the
user must predetermine the direction of the master mode
transmission before putting the calling address.
Below is the DDC2B+ function with channel 0, and the
manipulation of channel 1 is the same as channel 0.
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