NT68F62 Datasheet, PDF (29/57 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K Flash MTP Type)

NT68F62
13.2. Sync Processor Control Register:
Polarity: The detection of Hsync or Vsync polarity is
achieved by the hardware circuit that samples the sync
signal's voltage level periodically. Users can read the
HPOLI & VPOLI bits from the HVCON register, the bit = '1'
represents positive polarity and '0' represents negative
polarity. Furthermore, users can read the HSYNCI and
VSYNCI bits in the HVCON register to detect the H & V
sync input signal. Users can control the polarity of the H &
V sync output signal by writing the appropriate data to the
HPOLO and VPOLO bits in the HVCON register, '1'
represents positive polarity and '0', negative polarity.
Composite sync: Users have to determine whether the
incoming signal is separate sync or composite sync and set
the S/ C & ENHSEL / HSEL bit properly. If the input sync
signal is composite and after setting S/ C to '0', the sync
separator block will be activated (please refer to Figure
13.5). At the area of a Vsync pulse, there can exist Hsync
pulses or not. For the output of Hsync, users can activate
hardware to interpolate the Hsync pulses in that area by
clearing the INSEN bit. The width of these inserted pulses
is fixed at 2uS and the time interval is the same as the
previous one. According to the last Hsync pulse outside the
Vsync pulse duration, the hardware will arrange the interval
of these hardware interpolated pulses. These inserted
Hsync pulse perhaps have maximum phase deviation of
125 nS. The Vsync pulse can be extracted by hardware
from the composite Hsync signal and the delay time of the
output Vsync signal will be limited to less than 20ns. To
insert the Hsync pulse safely, the extracted Vsync pulse will
be widened about 9µs. Although , the system will insert the
Hsync pulse evenly, the last inserted Hsync pulse will have
a different frequency from the original ones.
The system will not implement this insertion function so
users must clear the INSEN bit in the SYNCON control
register to activate this function. After reset, the S/ C &
INSEN bits default value are HIGH and clear the VCNT |
HCNT counter latches to zero.
Sync output: In pin assignment, VSYNCO & HSYNCO
represent Vsync & Hsync output, which are shared with
P06 & P07 respectively. If ENVOUT & ENHOUT are set
to '0' in the HVCON register, P06 & P07 will act as
VSYNCO & HSYNCO output pins. When the input sync is a
separate signal, the V/HSYNCO will output the same signal
as the input without delay. But if the input sync is a
composite signal, the VSYNCO signal will have a fixed
delay time of about 20ns and the HSYNCO has a nonfixed
delay time of about 125ns.
Half frequency Input and output: In pin assignment, when
users set ENHALF bits to '0' in the HALFCON register, the
HALFHO pin will act as an output pin and output half of the
input signal in the HALFHI pin with 50% duty (see Figure
13.7). If set NOHALF to '0', HALFHO will output the same
signal in the HALFHI pin and the user can control its
polarity of output HALFHO by setting HALFPOL bit, '1' for
positive and '0' for negative polarity. After the chip is reset,
ENHALF 、 NOHALF & HALFPOL will be in the HIGH
state and P12 & P13 will act as I/O pins. It is recommended
to add a Schmitt Trigger buffer at the front of the HALFI pin.
Free run signal output: The user can select one of the free
running frequencies (listed below) outputting to HYSNCO &
VSYNCO pin by setting the FREQ0/1/2 bits. If the user
does not enable the H/VSYNCO by clearing the ENVOUT
or the ENHOUT bits, any setting of FREQ0/1/2 bits will be
invalid. After system reset, NT68F62 does not provide free
running frequency and both of the FREQ0/1/2 bits are set
to ' 1'. The free running frequency can be set according the
table below:
Free Running Freq.
1
2
3
4
5
FREQ2
0
0
0
0
1
1
1
FREQ1
0
0
1
1
0
1
1
FREQ0
0
1
0
1
0/1
0
1
Hsync Freq.
8M/256=31.2K
8M/4/9/5=44.4K
8M/128=62.5K
8M/4/5/5=80K
8M/4/2/11=90.9K
Vsync Freq.
Hsync/512=61.0Hz
Hsync/512=86.8Hz
Hsync/3/5/7/8=74.4Hz
Hsync/1024=78.1Hz
Hsync/1024=88.7Hz
Note
Refer to
Figure 13.7
Disabled Free
Run function
After System
Reset
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