NT68F62 Datasheet, PDF (40/57 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K Flash MTP Type)

NT68F62
15.3. DDC2B Slave Mode Bus Interface
Enable IIC and INTS: After the user clears the ENDDC to
‘0’, NT68F62 will enter into DDC1 mode, and it will switch
to DDC2B SLAVE mode when a low pulse is detected on
the SCL line. The DDC2B bus consists of two wires, SCL
and SDA; SCL is the data transmission clock and SDA is
the data line. NT68F62 will remind the user that the mode
has changed by generating an INTS interrupt. When users
set MD1/ ² to '1' at this time, the NT68F62 will return back
to DDC1 mode. (For DDC2B please refer to Figure 15.2.)
The figure exhibits what isimportant in IIC: START signal,
slave ADDRESS, transferred data (proceed byte by byte)
and a STOP signal.
Start condition: When SCL & SDA lines are at HIGH state,
an external device (master) may initiate communication by
sending a START signal (defined as SDA from high to low
transition while SCL is at high state). When there is a
START condition, NT68F62 will set the 'START' bit to '1'
and the user can poll this status bit to control the DDC2B
transmission at any time. This bit will stay as '1' until the
user clears it. After sending a START signal for DDC2B
communication, an external device can repeatedly send a
start condition without sending a STOP signal to terminate
this communication. This is used by the external device to
communicate with another slave or with the same slave in a
different mode (Read or Write mode) without releasing the
bus.
Address matched and INTA0: After the STARTcondition a
slave address is sent by an external device. When the IIC
bus interface changes to DDC2B mode, NT68F62 will act
as a receiver first to receive this one byte data. This
address data is 7 bits long followed by the eighth bit (R/W)
that the system receives as an address data from an
external device,
and stores in the CH0RXDAT register. The system
indicates the data transfer direction. The NT68F62
supports the 'A0' default address and another set of
addresses that can be accessed by writing to the
CH0ADDR register. The ‘A0’ default address of the DDC
channel 0 or 1 can be disabled by bit0 or bit1 at the
CH0/1_A0 control register ($3E). Upon receiving the calling
address from an external device, the system will compare
this received data with the default 'A0' address (if it is not
disabled) and the data in the CH0ADDR register. If either of
these addresses matches, the system will set the INTA0 bit
in the IRQ0 register. If the user sets the INTA0 bit to '1' (in
the IEIRQ0 register) in advanced and addresses match, the
NT68F62 will generate an INTA0 interrupt. Under the
address matching condition, the NT68F62 will send an
acknowledgement bit to an external device. If the address
does not match, the NT68F62 will not generate the INTA0
interrupt and will neglect the data change on the SDA line
in the future.
Data transmission direction: In the INTA0 interrupt servicing
routine, the user must check the LSB of the address data in
the CH0RXDAT register. According to the IIC bus protocol,
this bit indicates the DDC2B data transfer direction in later
transmission; '1' indicates a request for a 'READ MODE'
action (external master device read data from system), '0'
indicates a 'WRITE MODE' action (external master device
write data to system). For the timing about READ mode
and WRITE mode please refer to Figure 15.3 and Figure
15.4. The data transfer can proceed byte by byte in a
direction specified by the R/ W bit after a successful slave
address is received.
The system will switch to either 'READ' mode or 'WRITE'
mode automatically whichever is determined by this
direction bit.
INTSTOP
INTTX
TXACK
INTNAK
INTRX
INTA
R/W
STOP Detector
TXDAT
in
out
9 bits Shift Register
clk
ENDDC
RXDAT
Compare Logic
MD1/2
ADDR
INTS
MODE
DDC2BR [2..0]
Clock Generator
Figure 15.5. DDC Structure Block
SDA
VSYNC
SCL
40