NT68F62 Datasheet, PDF (23/57 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K Flash MTP Type)

NT68F62
12.3. PORT2: P20 - P27
PORT2, an 8-bit bi-directional I/O port (Figure 12.5), may be programmed as an input or output pin by the software control.
When setting the PT2DIR control bit to '0', its correspondent pin will act as an output pin. On the other hand, clear PT2DIR
bit to '1'and it will act as an input pin. When programmed as an input pin, it has an internal pull-up resistor. When
programmed as an output pin, the data to be output is latched to the port data register and output to the pin with a push-pull
structure. This port acts as an input port after reset.
Addr.
$0002
$0003
$0010
$0029
Register
PT2DIR
PT2
ENADC
CH1CON
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
FFH P27OE P26OE P25OE P24OE P23OE
FFH
P27
P26
P25
P24
P23
P22OE
P22
P21OE
P21
P20OE
W
P20
RW
FFH CSTA
―
―
―
ENADC3 ENADC2 ENADC1 ENADC0 W
FFH ENDDC MD1/ 2
SRW START
STOP
RXACK
TXACK
―
RW
12.4. PORT3: P30 - P31
PORT3 is a 2 bit bi-directional open-drain I/O port (Figure 12.6). Each pin of Port3 may be bit programmed as an input or
output port with open drain structure. When Port3 works as an output pin, the data to be output is latched to the port data
register and output to the pin. When Port3 pins have '1's written to them, users must connect PORT3 with the external
pulled-up resistor and then PORT3 can be used as an input (the input signal can be read). This port output is hiGH after
reset.
P30 、 P31 include Schmitt Trigger buffers for noise immunity and can be configured as the IIC pins SDA0 & SCL0
respectively. If ENDDC is set to LOW in the CH0DDC control register, P30、P31 will act as SDA0 & SCL0 I/O pins
respectively and will be of an open drain structure (Figure 12.6). After the chip is reset, this ENDDC bit will be in the HIGH
state and PORT3 will act as I/O pin.
Addr. Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0004
PT3
FFH
―
―
―
―
―
―
P31
P30
RW
$0024 CH0CON
FFH ENDDC MD1/ 2
SRW
START STOP RXACK TXACK
―
RW
I/O
Data Out
Data In
Figure 12.6. PORT3
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