NT68F62 Datasheet, PDF (22/57 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K Flash MTP Type)

NT68F62
12.2. Port1: P10 - P16
PORT10 - PORT16 is a 7-bit bi-directional CMOS I/O port
with PMOS as internal pull-up (Figure 12.1). Each bi-
directional I/O pin may be bit programmed as an input or
output port without software controlling the data direction
register. When Port1 works as an output, the data to be
output is latched to the port data register and output to the
pin. Port1 pins that have '1's written to them are pulled high
by the internal PMOS pull-ups. In this state they can be
used as inputs and then the input signals can be read. This
port output is high after reset.
P10 & P11 are shared with AD0 & AD1 input pins
respectively. If the ENADC0/ 1 bit in the ENADC control
register is cleared to LOW, the A/D converters will activate
simultaneously. After the chip is reset, ENADC0/1 bits will
be in the HIGH state and P10 - P11 will act as I/O pins.
P12、P13 are shared with the HALF SIGNALS input and
OUTPUT pins by accessing the OUTCON control register.
If the ENHALF bit is cleared to LOW, P13 will switch to
HALFHI pin (input pin) and P12 will switch to HALFHO pin
(output pin, Figure 12.3). For HALFHI & HALFHO pin
descriptions, please refer half frequency function in the H/V
sync processor paragraph. After the chip is reset, the
ENHALF bits will be in the HIGH state and P12、P13 will
act as I/O pins.
P14 is shared with the output pin of the self test pattern. If
users clear the PATTERN bit in the SYNCON control
register and the free running function has been activated,
the P14 will switch to be the output pin of the self test
pattern. This pattern output pin is of the push-pull structure.
After the chip is reset, the PATTERN bits will be in the
HIGH state and P14 will act as an I/O pin. (Refer to the
'Syncprocessor' section for more detailed information.)
P15 & P16 can be shared with the external interrupt INTE0
& INTE1 pins if the INTE0/1 bits are set in the control
register of the interrupt enable ($0018 & $001B). These
interrupt pins have 'Schmitt Trigger' input buffers. After the
chip is reset, INTE0/1 bits will be in the HIGH state and P15
& P16 will act as I/O pins.
Refer to the 'INTERRUPT CONTROLLER' paragraph
above for more details about the interrupt function.
Addr. Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0001
PT1
7FH
―
P16
P15
P14
P13
P12
P11
P10
RW
$000C FREECON FFH _{ENPAT PAT0}
―
―
―
FREQ2
FREQ1
FREQ0
W
$0010
ENADC
FFH
CSTA
―
―
―
ENADC3 ENADC2
ENADC1 ENADC0
W
$0018
IENMI
00H
―
―
―
―
―
―
INTE0 INTMUTE RW
$001B
IEIRQ2
00H
―
―
―
―
―
INTV
INTE1
INTMR RW
VDD
VDD
I/P
Data Input
Figure 12.4. Schmitt Input Structure
Data Out
Data OE
.
I/O
Data In
Figure 12.5. I/O Structure
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