NT68F62 Datasheet, PDF (18/57 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (32K Flash MTP Type)

NT68F62
DDC Channel 0/1 Maskable Interrupt Sources:
Interrupt
INTS INT
INTA INT
INTTX INT
INTRX INT
INTNAK INT
INTSTOP INT
Meaning
SCL Go-Low INT
Address Matched
INT
Transfer Buffer
Empty INT
Receiving Buffer
Overflow INT
No Acknowledge
INT
DDC2 Stop INT
Action
In DDC1 mode, it will be activated when the external device proceed a DDC2
communication. This action includes pulling the SCL line to ground or sending
out a 'START' condition directly. The system will respond to this action by
changing DDC1 mode to DDC2 slave mode.
It will be activated in DDC2 slave mode when the external device calls a
NT68F62 slave address. If this calling address matches the NT68F62 address,
the system will generate this interrupt to remind the user
It will be activated in DDC2 mode when the transmission buffer, IIC_TXDAT, is
empty in transmission mode.
It will be activated in DDC2 mode when the new data are stored in the
IIC_RXDAT register in receive mode.
In transmission mode, this interrupt will be activated when the NT68F62 has
send out one byte of data but the external device does not respond with an
acknowledgement bit to it.
In SLAVE mode, this interrupt will be activated when the NT68F62 receives a
'STOP' condition.
IRQ0
INTSTOP0
INTNAK0
INTRX0
INTTX0
INTA0
INTS0
IRQ1
INTSTOP1
INTNAK1
INTRX1
INTTX1
INTA1
INTS1
IRQ2
INTMR
INTE1
INTV
INTADC
NMIPOLL
INTMUTE
INTE0
IEIRQ0
IEIRQ1
IEIRQ2
IENMI
IRQ0
IRQ1
IRQ (to CPU 6502)
IRQ2
NMI (to CPU 6502)
Figure 11.1. Interrupt Controller Structure
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