LM3S611 Datasheet, PDF (9/409 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S611 Data Sheet
Figure 14-10. Master Burst RECEIVE (receiving m bytes) ............................................................................ 317
Figure 14-11. Master Burst RECEIVE after Burst SEND............................................................................... 318
Figure 14-12. Master Burst SEND after Burst RECEIVE............................................................................... 319
Figure 14-13. Slave Command Sequence..................................................................................................... 320
Figure 15-1. PWM Module Block Diagram................................................................................................... 344
Figure 15-2. PWM Count-Down Mode......................................................................................................... 345
Figure 15-3. PWM Count-Up/Down Mode ................................................................................................... 346
Figure 15-4. PWM Generation Example In Count-Up/Down Mode ............................................................. 346
Figure 15-5. PWM Dead-Band Generator ................................................................................................... 347
Figure 16-1. Pin Connection Diagram ........................................................................................................ 377
Figure 19-1. Load Conditions....................................................................................................................... 392
Figure 19-2. I²C Timing................................................................................................................................ 395
Figure 19-3. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement ................ 396
Figure 19-4. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer................................. 396
Figure 19-5. SSI Timing for SPI Frame Format (FRF=00), with SPH=1...................................................... 396
Figure 19-6. JTAG Test Clock Input Timing................................................................................................. 398
Figure 19-7. JTAG Test Access Port (TAP) Timing ..................................................................................... 398
Figure 19-8. JTAG TRST Timing ................................................................................................................. 398
Figure 19-9. External Reset Timing (RST)................................................................................................... 400
Figure 19-10. Power-On Reset Timing .......................................................................................................... 400
Figure 19-11. Brown-Out Reset Timing ......................................................................................................... 400
Figure 19-12. Software Reset Timing ............................................................................................................ 400
Figure 19-13. Watchdog Reset Timing .......................................................................................................... 401
Figure 19-14. LDO Reset Timing ................................................................................................................... 401
Figure 20-1. 48-Pin LQFP Package............................................................................................................. 402
April 27, 2007
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Preliminary