LM3S611 Datasheet, PDF (52/409 Pages) List of Unclassifed Manufacturers – Microcontroller

JTAG Interface
to 1 for PB7 and PC[3:0]) and enabling the alternate hardware function (setting GPIOAFSEL to 1
for PB7 and PC[3:0]) on the JTAG pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and
PC[3:0]in the GPIOAFSEL register. If the user does not require the JTAG port for debugging or
board-level testing, this provides five more GPIOs for use in the design.
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external
pull-down resistors connected to both of them at the same time. If both pins are pulled Low during
reset, the controller has unpredictable behavior. If this happens, remove one or both of the
pull-down resistors, and apply RST or power-cycle the part
In addition, it is possible to create a software sequence that prevents the debugger from connecting
to the Stellaris microcontroller. If the program code loaded into flash immediately changes the
JTAG pins to their GPIO functionality, the debugger does not have enough time to connect and
halt the controller before the JTAG pin functionality switches. This locks the debugger out of the
part. This can be avoided with a software routine that restores JTAG functionality using an
external trigger.
5.2.4.2
5.3
ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the
SWD session begins.
The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP
controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller
through the following states: Run Test Idle, Select DR, Select IR, Capture IR, Exit1 IR, Update IR,
Run Test Idle, Select DR, Select IR, Capture IR, Exit1 IR, Update IR, Run Test Idle, Select DR,
Select IR, and Test-Logic-Reset states.
Stepping through the JTAG TAP Instruction Register (IR) load sequences of the TAP state
machine twice without shifting in a new instruction enables the SWD interface and disables the
JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where
the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low
probability of this sequence occurring during normal operation of the TAP controller, it should not
affect normal performance of the JTAG interface.
Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the
user application changes these pins to their GPIO function, they must be configured back to their
JTAG functionality before JTAG communication can be restored. This is done by enabling the five
JTAG pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register.
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April 27, 2007
Preliminary