LM3S611 Datasheet, PDF (346/409 Pages) List of Unclassifed Manufacturers – Microcontroller

Pulse Width Modulator (PWM)
Figure 15-3. PWM Count-Up/Down Mode
Load
CompA
CompB
Zero
Load
Zero
A
B
Dir
15.2.3
BUp
AUp
BDown
ADown
PWM Signal Generator
The PWM generator takes these pulses (qualified by the direction signal), and generates two
PWM signals. In Count-Down mode, there are four events that can affect the PWM signal: zero,
load, match A down, and match B down. In Count-Up/Down mode, there are six events that can
affect the PWM signal: zero, load, match A down, match A up, match B down, and match B up.
The match A or match B events are ignored when they coincide with the zero or load events. If the
match A and match B events coincide, the first signal, PWMA, is generated based only on the match
A event, and the second signal, PWMB, is generated based only on the match B event.
For each event, the effect on each output PWM signal is programmable: it can be left alone
(ignoring the event), it can be toggled, it can be driven Low, or it can be driven High. These actions
can be used to generate a pair of PWM signals of various positions and duty cycles, which do or
do not overlap. Figure 15-4 shows the use of Count-Up/Down mode to generate a pair of
center-aligned, overlapped PWM signals that have different duty cycles.
Figure 15-4. PWM Generation Example In Count-Up/Down Mode
Load
CompA
CompB
Zero
PWMA
PWMB
In this example, the first generator is set to drive High on match A up, drive Low on match A down,
and ignore the other four events. The second generator is set to drive High on match B up, drive
Low on match B down, and ignore the other four events. Changing the value of comparator A
changes the duty cycle of the PWMA signal, and changing the value of comparator B changes the
duty cycle of the PWMB signal.
346
April 27, 2007
Preliminary