LM3S611 Datasheet, PDF (14/409 Pages) List of Unclassifed Manufacturers – Microcontroller

List of Registers
Register 25: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ................................... 236
Register 26: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................... 236
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ............................................................ 237
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 239
Register 1: UART Data (UARTDR), offset 0x000 ...................................................................................... 246
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 .............................. 248
Register 3: UART Flag (UARTFR), offset 0x018 ....................................................................................... 250
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ................................................. 252
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ........................................... 253
Register 6: UART Line Control (UARTLCRH), offset 0x02C ..................................................................... 254
Register 7: UART Control (UARTCTL), offset 0x030................................................................................. 256
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ................................................ 257
Register 9: UART Interrupt Mask (UARTIM), offset 0x038 ........................................................................ 258
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C............................................................ 260
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 ...................................................... 261
Register 12: UART Interrupt Clear (UARTICR), offset 0x044...................................................................... 262
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0.......................................... 263
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4.......................................... 264
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8.......................................... 265
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ......................................... 266
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0.......................................... 267
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4.......................................... 268
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8.......................................... 269
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ......................................... 270
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0............................................. 271
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4............................................. 272
Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8............................................. 273
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ............................................ 274
Synchronous Serial Interface (SSI) ............................................................................................. 275
Register 1: SSI Control 0 (SSICR0), offset 0x000 ..................................................................................... 287
Register 2: SSI Control 1 (SSICR1), offset 0x004 ..................................................................................... 289
Register 3: SSI Data (SSIDR), offset 0x008 .............................................................................................. 291
Register 4: SSI Status (SSISR), offset 0x00C ........................................................................................... 292
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 ......................................................................... 293
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ................................................................................ 294
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .................................................................... 295
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C.............................................................. 296
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020.............................................................................. 297
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0.................................................. 298
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4.................................................. 299
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8.................................................. 300
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ................................................. 301
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0.................................................. 302
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4.................................................. 303
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8.................................................. 304
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ................................................. 305
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0..................................................... 306
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4..................................................... 307
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April 27, 2007
Preliminary