LM3S611 Datasheet, PDF (256/409 Pages) List of Unclassifed Manufacturers – Microcontroller

Universal Asynchronous Receivers/Transmitters (UARTs)
Register 7: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are
written. If the UART is disabled during a transmit or receive operation, the current transaction is
completed prior to the UART stopping.
UART Control (UARTCR)
Offset 0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
Type RO
RO
RO
RO
Reset
0
0
0
0
RXE TXE LBE
reserved
UARTEN
RO
RO
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
R/W
0
0
1
1
0
0
0
0
0
0
0
0
Bit/Field
31:10
9
8
7
6:1
0
Name
reserved
RXE
TXE
LBE
reserved
UARTEN
Type
RO
R/W
R/W
R/W
RO
R/W
Reset
0
1
1
0
0
0
Description
Reserved bits return an indeterminate value, and should never
be changed.
UART Receive Enable
If this bit is set to 1, the receive section of the UART is enabled.
When the UART is disabled in the middle of a receive, it
completes the current character before stopping.
UART Transmit Enable
If this bit is set to 1, the transmit section of the UART is enabled.
When the UART is disabled in the middle of a transmission, it
completes the current character before stopping.
UART Loop Back Enable
If this bit is set to 1, the UNTX path is fed through the UNRX path.
Reserved bits return an indeterminate value, and should never
be changed.
UART Enable
If this bit is set to 1, the UART is enabled. When the UART is
disabled in the middle of transmission or reception, it completes
the current character before stopping.
256
April 27, 2007
Preliminary