LM3S611 Datasheet, PDF (213/409 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S611 Data Sheet
3. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn register.
4. For each sample in the sample sequence, configure the sample control bits in the
corresponding nibble in the ADCSSCTLn register. When programming the last nibble, ensure
that the END bit is set. Failure to set the END bit causes unpredictable behavior.
5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register.
6. Enable the Sample Sequencer logic by writing a 1 to the corresponding ASEN bit in the
ADCACTSS register.
11.4
Register Map
Table 11-2 lists the ADC registers. The offset listed is a hexadecimal increment to the register’s
address, relative to the ADC base address of 0x40038000.
Table 11-2. ADC Register Map
Offset Name
Reset
Type Description
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x020
0x028
0x030
0x040
0x044
0x048
0x04C
0x060
0x064
0x068
0x06C
0x080
0x084
0x088
ADCACTSS
ADCRIS
ADCIM
ADCISC
ADCOSTAT
ADCEMUX
ADCUSTAT
ADCSSPRI
ADCPSSI
ADCSAC
ADCSSMUX0
ADCSSCTL0
ADCSSFIFO0
ADCSSFSTAT0
ADCSSMUX1
ADCSSCTL1
ADCSSFIFO1
ADCSSFSTAT1
ADCSSMUX2
ADCSSCTL2
ADCSSFIFO2
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00003210
-
0x00000000
0x00000000
0x00000000
0x00000000
0x00000100
0x00000000
0x00000000
0x00000000
0x00000100
0x00000000
0x00000000
0x00000000
R/W
RO
R/W
R/W1C
R/W1C
R/W
R/W1C
R/W
WO
R/W
R/W
R/W
RO
RO
R/W
R/W
RO
RO
R/W
R/W
RO
Active sample sequencer
Raw interrupt status and clear
Interrupt mask
Interrupt status and clear
Overflow status
Event multiplexer select
Underflow status
Sample sequencer priority
Processor sample sequence initiate
Sample averaging control
Sample sequence input multiplexer select 0
Sample sequence control 0
Sample sequence result FIFO 0
Sample sequence FIFO 0 status
Sample sequence input multiplexer select 1
Sample sequence control 1
Sample sequence result FIFO 1
Sample sequence FIFO 1 status
Sample sequence input multiplexer select 2
Sample sequence control 2
Sample sequence result FIFO 2
See
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April 27, 2007
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Preliminary