LM3S611 Datasheet, PDF (249/409 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S611 Data Sheet
Bit/Field
2
Name
BE
Type
RO
Reset
0
1
PE
RO
0
0
FE
RO
0
Write-Only Error Clear (UARTECR) Register
31:8
reserved
WO
0
7:0
DATA
WO
0
Description
UART Break Error
This bit is set to 1 when a break condition is detected, indicating
that the received data input was held Low for longer than a full-
word transmission time (defined as start, data, parity, and stop
bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the
top of the FIFO. When a break occurs, only one 0 character is
loaded into the FIFO. The next character is only enabled after
the receive data input goes to a 1 (marking state) and the next
valid start bit is received.
UART Parity Error
This bit is set to 1 when the parity of the received data character
does not match the parity defined by bits 2 and 7 of the
UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
UART Framing Error
This bit is set to 1 when the received character does not have a
valid stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the
top of the FIFO.
Reserved bits return an indeterminate value, and should never
be changed.
A write to this register of any data clears the framing, parity,
break and overrun flags.
April 27, 2007
249
Preliminary