LM3S611 Datasheet, PDF (211/409 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S611 Data Sheet
11.2.2
11.2.2.1
11.2.2.2
11.2.2.3
11.2.3
11.2.4
11.2.5
Module Control
Outside of the Sample Sequencers, the remainder of the control logic is responsible for tasks such
as interrupt generation, sequence prioritization, and trigger configuration.
Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider is
configured automatically by hardware when the system XTAL is selected. The automatic clock
divider configuration targets 16.667 MHz operation for all Stellaris devices.
Interrupts
The Sample Sequencers dictate the events that cause interrupts, but they don't have control over
whether the interrupt is actually sent to the interrupt controller. The ADC module's interrupt signal
is controlled by the state of the MASK bits in the ADC Interrupt Mask (ADCIM) register. Interrupt
status can be viewed at two locations: the ADC Raw Interrupt Status (ADCRIS) register, which
shows the raw status of a Sample Sequencer's interrupt signal, and the ADC Interrupt Status
and Clear (ADCISC) register, which shows the logical AND of the ADCRIS register’s INR bit and
the ADCIM register’s MASK bits. Interrupts are cleared by writing a 1 to the corresponding IN bit in
ADCISC.
Prioritization
When sampling events (triggers) happen concurrently, they are prioritized for processing by the
values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in
the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active Sample
Sequencer units with the same priority do not provide consistent results, so software must ensure
that all active Sample Sequencer units have a unique priority value.
Sampling Events
Sample triggering for each Sample Sequencer is defined in the ADC Event Multiplexer Select
(ADCEMUX) register. The external peripheral triggering sources vary by Stellaris family member,
but all devices share the "Controller" and "Always" triggers. Software can initiate sampling by
setting the CH bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register.
When using the "Always" trigger, care must be taken. If a sequence's priority is too high, it is
possible to starve other lower priority sequences.
Hardware Sample Averaging Circuit
Higher precision results can be generated using the hardware averaging circuit, however, the
improved results are at the cost of throughput. Up to 64 samples can be accumulated and
averaged to form a single data entry in the sequencer FIFO. Throughput is decreased
proportionally to the number of samples in the averaging calculation. For example, if the averaging
circuit is configured to average 16 samples, the throughput is decreased by a factor of 16.
By default the averaging circuit is off and all data from the converter passes through to the
sequencer FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control
(ADCSAC) register (see page 224). There is a single averaging circuit and all input channels
receive the same amount of averaging whether they are single-ended or differential.
Analog-to-Digital Converter
The converter itself generates a 10-bit output value for selected analog input. Special analog pads
are used to minimize the distortion on the input.
Test Modes
There is a user-available test mode that allows for loopback operation within the digital portion of
the ADC module. This can be useful for debugging software without having to provide actual
April 27, 2007
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Preliminary