NRF9E5 Datasheet, PDF (79/104 Pages) List of Unclassifed Manufacturers – 433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC

PRODUCT SPECIFICATION
nRF9 E5 Single Chip Transceiver with Embedded Microcontroller and ADC
Bit
T2CON.7
T2CON.6
T2CON.5
T2CON.4
T2CON.3
T2CON.2
T2CON.1
T2CON.0
Function
TF2 - Timer 2 overflow flag. Hardware will set TF2 when Timer 2 overflows from
0xFFFF. TF2 must be cleared to 0 by the software. TF2 will only be set to a 1 if RCLK and
TCLK are both cleared to 0. Writing a 1 to TF2 forces a Timer 2 interrupt if enabled.
EXF2 - Timer 2 external flag. Hardware will set EXF2 when a reload or capture is caused
by a high-to-low transition on the t2ex pin, and EXEN2 is set. EXF2 must be cleared to 0
by the software. Writing a 1 to EXF2 forces a Timer 2 interrupt if enabled.
RCLK - Receive clock flag. Determines whether Timer 1 or Timer 2 is used for Serial port
timing of received data in serial mode 1 or 3. RCLK = 1 selects Timer 2 overflow as the
receive clock. RCLK = 0 selects Timer 1 overflow as the receive clock.
TCLK - Transmit clock flag. Determines whether Timer 1 or Timer 2 is used for Serial port
timing of transmit data in serial mode 1 or 3. TCLK =1 selects Timer 2 overflow as the
transmit clock. TCLK = 0 selects Timer 1 overflow as the transmit clock.
EXEN2 - Timer 2 external enable. EXEN2 = 1 enables capture or reload to occur as a result
of a high-to-low transition on t2ex, if Timer 2 is not generating baud rates for the serial
port. EXEN2 = 0 causes Timer 2 to ignore all external events at t2ex.
TR2 - Timer 2 run control flag. TR2 = 1 starts Timer 2. TR2 = 0 stops Timer 2.
C/T2 - Counter/timer select. C/T2 = 0 selects a timer function for Timer 2. C/T2 = 1 selects
a counter of falling transitions on the t2 pin. When used as a timer, Timer 2 runs at four
clocks per increment or twelve clocks per increment as programmed by CKCON.5, in all
modes except baud-rate generator mode. When used in baud-rate generator mode, Timer 2
runs at two clocks per increment, independent of the state of CKCON.5.
CP/RL2 - Capture/reload flag. When CP/RL2 = 1, Timer 2 captures occur on high-to-low
transitions of t2ex, if EXEN2 = 1. When CP/RL2 = 0, auto-reloads occur when Timer 2
overflows or when high-to-low transitions occur on t2ex, if EXEN2 = 1. If either RCLK or
TCLK is set to 1, CP/RL2 will not function, and Timer 2 will operate in auto-reload mode
following each overflow.
Table 68 T2CON Register – SFR 0xC8.
18.8.3.1 Timer 2 Mode Control
Table 69 summarizes how the SFR bits determine the Timer 2 mode.
RCLK
0
0
1
X
X
TCLK
0
0
X
1
X
CP/RL2
1
0
X
X
X
TR2 Mode
1
16-bit timer/counter with capture
1
16-bit timer/counter with auto-reload
1
Baud-rate generator
1
Baud-rate generator
0
Off
Table 69 Timer 2 Mode Control Summary.
18.8.3.2 16-Bit Timer/Counter Mode
Figure 21 Timer 2 – Timer/Counter with Capture illustrates how Timer 2 operates in
timer/counter mode with the optional capture feature. The C/T2 bit determines whether
the 16-bit counter counts clock cycles (divided by 4 or 12), or high-to-low transitions on
the t2 pin. The TR2 bit enables the counter. When the count increments from 0xFFFF,
the TF2 flag is set, and t2_out goes high for one clock cycle.
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone [phone] - Fax [phone]
Revision: 1.1
Page 79 of 104
June 2004