NRF9E5 Datasheet, PDF (43/104 Pages) List of Unclassifed Manufacturers – 433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC

PRODUCT SPECIFICATION
nRF9 E5 Single Chip Transceiver with Embedded Microcontroller and ADC
13 SPI
nRF9E5 SPI is a simple single buffered master. The 3 data lines of the SPI bus (MISO,
SCK and MOSI) are multiplexed (by writing to register SPI_CTRL) between the GPIO
pins (lower 3 bits of P1) and the RF transceiver and AD converter subsystems. The SPI
hardware does not generate any chip select signal. The bootstrap loader uses EECSN
(GPIO P0.3) as chip select for the boot EEPROM. On-chip GPIO P2.3 is dedicated as
chip select for the RF transceiver and AD converter subsystems. GPIO pins from port 0
may be used as chip selects for other external SPI slaves.
The SPI hardware is controlled by SFR’s SPI_DATA (0xb2), SPI_CTRL (0xb3) and
SPICLK (0xb4) as explained in Table 33 below.
Addr
SFR
(hex)
B2
B3
B4
R/W #bit Init Name
(hex)
Function
R/W 8
R/W 2
R/W 4
0 SPI_DATA SPI data input/output
0 SPI_CTRL
00 -> SPI not used no clock generated
01 -> SPI connected to port P1 (as for booting)
(see also Table 11 Port 1 (P1) functions)
10 -> SPI connected to the nRF905 transceiver
(see Table 15 P2 (RADIO) register )
0 SPICLK
Divider factor from CPU clock to SPI clock
0000: 1/2 of CPU clock frequency
0001: 1/2 of CPU clock frequency
0010: 1/4 of CPU clock frequency
0011: 1/8 of CPU clock frequency
0100: 1/16 of CPU clock frequency
0101: 1/32 of CPU clock frequency
0110: 1/64 of CPU clock frequency
other: 1/64 of CPU clock frequency
Table 33 SPI control and data SFR-registers.
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone [phone] - Fax [phone]
Revision: 1.1
Page 43 of 104
June 2004