NRF9E5 Datasheet, PDF (58/104 Pages) List of Unclassifed Manufacturers – 433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC

PRODUCT SPECIFICATION
nRF9 E5 Single Chip Transceiver with Embedded Microcontroller and ADC
17.2 Additional Power Down Modes
An instruction that sets the CK_CTRL (SFR 0xB6) to a non zero value causes the
nRF9E5 to enter power down mode when that instruction completes. In power down
mode, CPU processing is suspended, while internal registers and memories maintain
their current data. The CPU will perform a controlled shutdown of clock and power
regulators as requested by CK_CTRL.
The device can only be restarted from an event on a P0 GPIO pin, an RTC wakeup or a
Watchdog reset. Activation of any enabled wakeup source causes the hardware to clear
the CK_CTRL bit and terminate power down mode. If there is an enabled interrupt
associated with the wakeup even, the CPU executes the ISR associated with that
interrupt immediately after power and clocks are restored. The RETI instruction at the
end of the ISR returns the CPU to the instruction following the one that put the nRF9E5
into power down mode. A watchdog reset causes the nRF9E5 to exit power down mode,
reset internal registers, execute its reset sequence and begin program execution at the
standard reset vector address 0x0000.
Addr
SFR
B6
R/W #bit
W
3
R
1
Init Name
Hex
0 CK_CTRL
- CK_CTRL
Function
Set power down according to Table 51.
Read LFCK clock in LSB. Other bits are
unpredictable.
Table 50 CK_CTRL register – SFR 0xB6.
Note: Before writing the CK_CTRL register, make sure that the busy bit of
RTC/Watchdog SFR 0xAD, bit 4 (page 54) is not set
Note: When using power down modes where the CKLF source is LP_OSC, the startup
time may be so long that the CPU may loose the corresponding interrupt.
CK_CTRL
(write)
000
001
010
011
1--
Function
Normal operation, active
Light power down
Moderate power down
Standby mode
Deep power down
CKLF
source
XTAL
XTAL
XTAL
LP_OSC
LP_OSC
XTAL
Osc
On
On
On
On
Off
Typical
Current
1 mA
0.4 mA
125 µA
25 µA
2.5 µA
Typical
Startup
-
2.5 µs
7 µs
150 µs
1000 µs
Table 51 Power down modes.
The table above shows typical startup time from interrupt. For GPIO the debounce time
must be added, but during debounce the device is still in power down.
17.2.1 Startup Time From Reset
Startup time consists of a number of LP_OSC cycles + a number of XTAL clock
cycles. f_{LP_OSC} may vary from 1 to 5.5kHz over voltage and temperature.
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone [phone] - Fax [phone]
Revision: 1.1
Page 58 of 104
June 2004