NRF9E5 Datasheet, PDF (15/104 Pages) List of Unclassifed Manufacturers – 433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC

PRODUCT SPECIFICATION
nRF9 E5 Single Chip Transceiver with Embedded Microcontroller and ADC
Port 0 is controlled by SFR-registers 0x80, 0x93, 0x94 and 0x95 listed in the table
below.
Addr
SFR
(hex)
80
93
94
95
R/W
R/W
R/W
R/W
R/W
#bit Init Name
Function
value
(hex)
8
FF P0
Port 0, pins P07 to P00
8
00 P0_DRV High drive strength for each bit of Port 0
0: Enable, 1: Disable
(See 6.2.1 below for a description)
8
FF P0_DIR Direction for each bit of Port 0
0: Output, 1: Input
Direction is overridden if alternate function is
selected for a pin.
8
00 P0_ALT Select alternate functions for each pin of P0, if
corresponding bit in P0_ALT is set, as listed in
Table 9 Port 0 (P0) functions.
Table 10 Port 0 control and data SFR-registers.
6.2.1 High Current Drive Capability
Odd numbered bits will source high current when the corresponding bit in P0_DRV is
set, where as even number bits will sink high current when the corresponding bit in
P0_DRV is set.
6.3 Port 1 (P1 or SPI port)
The P1 port consists of 4 pins, one of which is a hardwired input. The primary function
of the P1 port (when SPI_CTRL is 01) is a SPI master port. The pin EECSN is used as a
chip select for the boot EEPROM, the GPIO bits in port P0 may be used as chip select(s)
for other SPI devices.
When not used as SPI port, P1_ALT.0 will force SCK (P1.0) to be the timer T2 input;
MOSI (P1.1) is now a GPIO. When P0_ALT.0 is 0, also SCK (P1.0) is a GPIO.
MISO (P1.2) is always an input. That is P1_DIR.2 and P1_ALT.2 are ignored.
EECSN (P1.3) is always a GPIO. It will be activated by the default boot loader after
reset and should be connected to the CSN of the boot flash.
Pin
SCK
MOSI
MISO
EECSN
SPI_CTRL = 01
SPI.clock
Out
SPI.dataout
Out
SPI.datain
In
P1.3
Out
P1_ALT.n = 1
T2
In
P1.1
I/O²
P1.2
In
P1.3
I/O²
SPI_CTRL != 01
P1_ALT.n = 0
P1_DIR.n = 0
P1_DIR.n = 1
P1.0 In
P1.0
Out
P1.1 In
P1.1
Out
P1.2 In
P1.2
In
P1.3 In
P1.3
Out
Table 11 Port 1 (P1) functions.
2 _{P1.1 and P1.3 are actually under control of P1_DIR.1 and P1_DIR.3 even when P1_ALT.1 or P1_ALT.3}
are 1, since there are no alternate functions for these pins.
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone [phone] - Fax [phone]
Revision: 1.1
Page 15 of 104
June 2004