NRF9E5 Datasheet, PDF (50/104 Pages) List of Unclassifed Manufacturers – 433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC

PRODUCT SPECIFICATION
nRF9 E5 Single Chip Transceiver with Embedded Microcontroller and ADC
15.6 Interrupt Latency
Interrupt response time depends on the current state of the CPU. The fastest response
time is five instruction cycles: one to detect the interrupt, and four to perform the
LCALL to the ISR. The maximum latency (thirteen instruction cycles) occurs when the
CPU is currently executing an RETI instruction followed by a MUL or DIV instruction.
The thirteen instruction cycles in this case are: one to detect the interrupt, three to
complete the RETI, five to execute the DIV or MUL, and four to execute the LCALL to
the ISR.
For the maximum latency case, the response time is 13 x 4 = 52clock cycles.
15.7 Interrupt Latency from Power Down State.
The nRF9E5 may be set into Power Down state by writing a non zero value to SFR
0xB6, register CK_CTRL. The CPU will then perform a controlled shutdown of clock
and power regulator depending on what mode was selected. The system can only be
restarted from an RTC wakeup, a GPIO wakeup or a Watchdog reset. If a wakeup
interrupt is enabled, the startup time for regulators and clocks will be added to the
interrupt latency. See 17.2.1 Startup Time From Reset
15.8 Single-Step Operation
The nRF9E5 interrupt structure provides a way to perform single-step program
execution. When exiting an ISR with an RETI instruction, the CPU will always execute
at least one instruction of the task program. Therefore, once an ISR is entered, it cannot
be re-entered until at least one program instruction is executed. To perform single-step
execution, program one of the external interrupts (for example, INT0_N) to be level
sensitive and write an ISR for that interrupt that terminates as follows:
JNB TCON.1,$ ;
JB TCON.1,$ ;
RETI ;
wait for high on INT0_N
wait for low on INT0_N
return for ISR
The CPU enters the ISR when INT0_N goes low, then waits for a pulse on INT0_N.
Each time INT0_N is pulsed, the CPU exits the ISR, executes one program instruction,
then re-enters the ISR.
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Revision: 1.1
Page 50 of 104
June 2004