NRF9E5 Datasheet, PDF (49/104 Pages) List of Unclassifed Manufacturers – 433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC

PRODUCT SPECIFICATION
nRF9 E5 Single Chip Transceiver with Embedded Microcontroller and ADC
15.5 Interrupt Sampling
The internal timers and serial port generate interrupts by setting their respective SFR
interrupt flag bits. The CPU samples external interrupts once per instruction cycle, at the
rising edge of CPU_clk at the end of cycle C4.
The INT0_N and INT1_N signals are both active low and can be programmed through
the IT0 and IT1 bits in the TCON SFR to be either edge-sensitive or level-sensitive. For
example, when IT0 = 0, INT0_N is level-sensitive and the CPU sets the IE0 flag when
the INT0_N pin is sampled low. When IT0 = 1, INT0_N is edge-sensitive and the CPU
sets the IE0 flag when the INT0_N pin is sampled high then low on consecutive
samples. To ensure that edge-sensitive interrupts are detected, the corresponding ports
should be held high for four clock cycles and then low for four clock cycles. Level-
sensitive interrupts are not latched and must remain active until serviced.
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone [phone] - Fax [phone]
Revision: 1.1
Page 49 of 104
June 2004