NT5SV64M4AT Datasheet, PDF (39/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Read Cycle
Symbol
Parameter
t_OH
Data Out Hold Time
t_LZ
t_HZ3
t_HZ2
t_DQZ
Data Out to Low Impedance Time
Data Out to High Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
-7K
Min.
Max.
—
—
2.7
—
0
—
3
5.4
3
5.4
2
—
-75B
Min.
Max.
—
—
2.7
—
0
—
3
5.4
3
6
2
—
-8B
Min.
Max.
2.5
—
3
—
0
—
3
6
3
6
2
—
Units Notes
ns
1
ns 2, 4
ns
ns
3
ns
3
CK
1. AC Output Load Circuit A.
2. AC Output Load Circuit B.
3. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
4. Data Out Hold Time with no load must meet 1.8ns (-75H, -75D, -75A).
Refresh Cycle
Symbol
Parameter
t_REF
t_SREX
Refresh Period
Self Refresh Exit Time
1. 8192 a uto refresh cycles.
-7K
Min.
Max.
—
64
10
—
-75B
Min.
Max.
—
64
10
—
-8B
Min.
Max.
—
64
10
—
Units Notes
ms
1
ns
Write Cycle
Symbol
Parameter
t_DS
t_{D H}
t_DPL
t_DAL3
t_DAL2
t_DQW
Data In Set-up Time
Data In Hold Time
Data input to Precharge
Data In to Active Delay
CAS Latency = 3
Data In to Active Delay
CAS Latency = 2
DQM Write Mask Latency
-7K
Min.
Max.
1.5
—
0.8
—
15
—
5
—
5
—
0
—
-75B
Min.
Max.
1.5
—
0.8
—
15
—
5
—
5
—
0
—
-8B
Min.
Max.
2
—
1
—
20
—
5
—
5
—
0
—
Units
ns
ns
ns
CK
CK
CK
REV 1.0
May, 2001
39
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