NT5SV64M4AT Datasheet, PDF (24/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the
device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the
Data-in to Precharge delay, t_DPL.
Precharge Termination of a Burst Write
(Burst Length = 8, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND ^NOP
NOP
WRITE Ax₀
NOP
NOP
NOP
Precharge A
NOP
NOP
DQM
CAS latency = 2
t_CK2, DQs
CAS latency = 3
t_CK3, DQs
t_DPL ‡
DIN Ax₀
DIN Ax ₁
DIN Ax₂
DIN Ax₀
DIN Ax ₁
t_DPL‡
DIN Ax₂
‡ t_DPL is an asynchronous timing and may be completed in one or two clock cycles
depending on clock cycle time.
REV 1.0
May, 2001
24
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