NT5SV64M4AT Datasheet, PDF (15/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs
must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data
contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is pre-
sented on the DQ pins before the Read Command is initiated will actually be written to the memory.
Minimum Write to Read Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND ^{WRITE A}
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
t_CK2, DQs
DIN A ₀
CAS latency = 3
t_CK3, DQs
DIN A₀
DOUT B ₀
DOUT B₁
DOUT B ₂
DOUT B₃
DOUT B ₀
DOUT B₁
DOUT B ₂
DOUT B₃
: “H” or “L”
Input data for the Write is masked.
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
REV 1.0
May, 2001
15
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.