NT5SV64M4AT Datasheet, PDF (19/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it can be interrupted
by a Read or Write Command to a different bank. If the command is issued before auto-precharge begins then the precharge
function will begin with the new command. The bank being auto-precharged may be reactivated after the delay t_RP.
Burst Read with Auto-Precharge Interrupted by Read
(Burst Length = 4, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND
READ A
Auto-Precharge
NOP
CAS latency = 2
t_CK2, DQs
CAS latency = 3
t_CK3, DQs
READ B
NOP
DOUT A ₀
t_RP‡
DOUT A₁
NOP
*
DOUT B ₀
t_RP‡
DOUT A₀
DOUT A ₁
NOP
DOUT B ₁
*
DOUT B ₀
NOP
DOUT B₂
DOUT B₁
NOP
DOUT B ₃
DOUT B₂
NOP
DOUT B ₃
*^{Bank can be reactivated at completion of t RP.}
‡ t_RP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention.
Burst Read with Auto-Precharge Interrupted by Write
(Burst Length = 8, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND
READ A
Auto-Precharge
NOP
CAS latency = 2
t_CK2, DQs
NOP
NOP
DOUT A ₀
WRITE B
NOP
D IN B₀
t_RP‡
DIN B ₁
NOP
*
D IN B₂
NOP
D IN B ₃
NOP
D IN B₄
DQM
*^{Bank can be reactivated at completion of t RP.}
‡ t_RP is a function of clock cycle time and speed sort. .
See the Clock Frequency and Latency table .
REV 1.0
May, 2001
19
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