NT5SV64M4AT Datasheet, PDF (16/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Non-Minimum Write to Read Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND ^{WRITE A}
NOP
READ B
NOP
CAS latency = 2
t_CK2, DQs
DIN A ₀
CAS latency = 3
t_CK3, DQs
DIN A₀
DIN A ₁
DIN A ₁
NOP
NOP
NOP
NOP
NOP
DOUT B₀
DOUT B ₁
DOUT B₂
DOUT B ₃
DOUT B ₀
DOUT B₁
DOUT B₂
DOUT B ₃
: “H” or “L”
Input data for the Write is masked.
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
REV 1.0
May, 2001
16
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