NT5SV64M4AT Datasheet, PDF (37/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
AC Characteristics (T_A = 0 to +70°C, V_DD = 3.3V ± 0.3V)
1. An initial pause of 200µs, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must
be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation.
2. The Transition time is measured between V_IH and V_IL (or between V_IL and V_IH)
3. In addition to meeting the transition rate specification, the clock and CKE must transit between V_IH and V_IL (or between V_IL
and V_IH) in a monotonic manner.
4. Load Circuit A: AC timing tests have V_IL = 0.4 V and V_IH = 2.4 V with the timing referenced to the 1.40V crossover point
5. Load Circuit A: AC measurements assume t_T = 1.0ns.
6. Load Circuit B: AC timing tests have V_IL = 0.8 V and V_IH = 2.0 V with the timing referenced to the 1.40V crossover point
7. Load Circuit B: AC measurements assume t_T = 1.2ns.
.
AC Characteristics Diagrams
Clock
Input
Output
t_CKL
t_SETUP
t_HOLD
1.4V
t_AC
t_LZ
t_CKH
t_T
V_IH
1.4V
V_IL
t_{O H}
1.4V
Output
Z_o = 50Ω
AC Output Load Circuit (A)
Vtt = 1.4V
50Ω
50pF
Output
Z_o = 50Ω
AC Output Load Circuit (B)
50pF
REV 1.0
May, 2001
37
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