NT5SV64M4AT Datasheet, PDF (20/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing auto-
precharge cannot be reactivated until t_DAL, Data-in to Active delay, is satisfied.
Burst Write with Auto-Precharge
(Burst Length = 2, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND
WRITE A
Auto-Precharge
NOP
CAS latency = 2
t_CK2, DQs
DIN A ₀
DIN A₁
CAS latency = 3
t_CK3, DQs
DIN A₀
DIN A₁
NOP
NOP
t_DAL ‡
t_DAL‡
NOP
NOP
NOP
NOP
NOP
*
*
*^{Bank can be reactivated at completion of tDAL.}
‡ t_DAL is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command to the same bank.
It can be interrupted by a Read or Write Command to a different bank, however. The interrupting command will terminate the
write. The bank undergoing auto-precharge can not be reactivated until t_DAL is satisfied.
Burst Write with Auto-Precharge Interrupted by Write
(Burst Length = 4, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND
WRITE A
Auto-Precharge
CAS latency = 3
t_CK3, DQs
DIN A ₀
NOP
WRITE B
NOP
DIN A ₁
t_DAL‡
DIN B ₀
DIN B ₁
NOP
DIN B₂
NOP
*
DIN B₃
NOP
NOP
NOP
*^{Bank can be reactivated at completion of tDAL.}
‡ t_DAL is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
REV 1.0
May, 2001
20
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