NT5SV64M4AT Datasheet, PDF (12/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance
state to avoid data contention on the DQ bus. If a Read Command will issue data on the first or second clocks cycles of the
write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ
bus.
Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
DQM
DQM high for CAS latency = 2 only.
Required to mask first bit of READ data.
COMMAND ^NOP
READ A
WRITE A
NOP
NOP
NOP
CAS latency = 2
t _CK2, DQs
CAS latency = 3
t _CK3, DQs
: “H” or “L”
DIN A ₀
DIN A ₁
DIN A ₂
DIN A ₃
DIN A ₀
DIN A ₁
DIN A ₂
DIN A ₃
NOP
NOP
NOP
REV 1.0
May, 2001
12
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