NT5SV64M4AT Datasheet, PDF (21/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Burst Write with Auto-Precharge Interrupted by Read
(Burst Length = 4, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND
WRITE A
Auto-Precharge
NOP
CAS latency = 3
t_CK3, DQs
DIN A₀
DIN A₁
NOP
READ B
DIN A₂
NOP
NOP
t_DAL ‡
NOP
DOUT B ₀
NOP
*
DOUT B₁
NOP
DOUT B ₂
* ^{Bank A can be reactivated at completion of t}DAL ^.
‡ t_DAL is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered
when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to pre-
charge each bank separately or all banks simultaneously. Three address bits, A10, BA0, and BA1, are used to define which
bank(s) is to be precharged when the command is issued.
Bank Selection for Precharge by Address Bits
A10
LOW
HIGH
Bank Select
BA0, BA1
DON’T CARE
Precharged Bank(s)
Single bank defined by BA0, BA1
All Banks
For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a
delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is
known as t_DPL, Data-in to Precharge delay.
After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be
executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Pre-
charge time (t_RP).
REV 1.0
May, 2001
21
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