NT5SV64M4AT Datasheet, PDF (28/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Clock Suspend Mode
During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the banks
is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or “freezes”
any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and
the time at which the SDRAM’s operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands
that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE
returns high to when Clock Suspend mode is exited.
When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto
the DQ pins will be actively held valid until Clock Suspend mode is exited.
Clock Suspend during a Read Cycle
T0
CK
CKE
COMMAND ^NOP
T1
T2
READ A
NOP
T3
NOP
(Burst Length = 4, CAS Latency = 2)
T4
T5
T6
T7
T8
A one clock delay before
suspend operation starts
A one clock delay to exit
the Suspend command
NOP
NOP
DQs
: “H” or “L”
DOUT A ₀
DOUT A ₁
DOUT element at the DQs when the
suspend operation starts is held valid
DOUT A₂
If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the Clock Sus-
pend mode is exited.
Clock Suspend during a Write Cycle
(Burst Length = 4, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
CKE
COMMAND ^NOP
WRITE A
NOP
NOP
A one clock delay before
suspend operation starts
A one clock delay to exit
the Suspend command
NOP
NOP
DQs
: “H” or “L”
DIN A₀
DIN A₁
DIN A₂
DIN A₃
DIN is masked during the Clock Suspend Period
REV 1.0
May, 2001
28
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