NT5SV64M4AT Datasheet, PDF (22/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Burst Read Followed by the Precharge Command
(Burst Length = 4, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND ^{READ Ax}0
NOP
CAS latency = 3
t_CK2, DQs
NOP
NOP
NOP
Precharge A
NOP
t_RP
NOP
*^‡
DOUT Ax₀ DOUT Ax₁ DOUT Ax₂ D O U T A x₃
NOP
* ^{Bank A can be reactivated at completion of tRP.}
‡ t_{R P} is a function of clock cycle and speed sort.
Burst Write Followed by the Precharge Command
(Burst Length = 2, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND NOP
CAS latency = 2
t_CK2, DQs
Activate
Bank Ax
NOP
WRITE Ax₀
NOP
NOP
t_DPL‡
Precharge A
NOP
t_RP‡
NOP
*
DIN Ax ₀
DIN Ax₁
*^{Bank can be reactivated at completion of t RP.}
‡ t_DPL and t _RP are functions of clock cycle and speed sort.
See the Clock Frequency and Latency table.
REV 1.0
May, 2001
22
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