M14D128168A Datasheet, PDF (6/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D128168A (2M)
Operation Temperature Condition (TC) -40°C~95°C
DC Specifications
(IDD values are for the operation range of Voltage and Temperature)
Parameter
Symbol
Test Condition
Operating Current
(Active - Precharge)
IDD0
Operating Current
(Active - Read -
Precharge)
IDD1
One bank;
t_CK = t_CK (IDD), t_RC = t_RC (IDD), t_RAS = t_RAS (IDD)min;
CKE is High, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
One bank; I_OUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
t_CK = t_CK (IDD), t_RC = t_RC (IDD),
t_RAS = t_RAS (IDD)min, t_RCD = t_RCD (IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
Precharge
Power-Down
Standby Current
IDD2P
All banks idle;
t_CK = t_CK (IDD); CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge Quiet
Standby Current
IDD2Q
All banks idle;
t_CK = t_CK (IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Idle Standby Current IDD2N
All banks idle;
t_CK = t_CK (IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Version
Unit
-1.8
-2.5
85
75
mA
100
95
mA
12
12
mA
55
50
mA
55
50
mA
All banks open;
Fast PDN Exit
45
Active Power-down
Standby Current
IDD3P
t_CK = t_CK (IDD); CKE is LOW;
Other control and address bus inputs
MRS(12) = 0
are STABLE;
Slow PDN Exit
18
Data bus input are FLOATING
MRS(12) = 1
All banks open;
Active Standby
Current
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
IDD3N CKE is HIGH, CS is HIGH between valid commands;
80
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
All banks open, continuous burst Reads, I_OUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0;
Operation Current
(Read)
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
IDD4R _{CKE is HIGH, CS is HIGH between valid commands;}
210
Address bus inputs are SWITCHING;
Data pattern is the same as IDD4W;
All banks open, continuous burst Writes;
BL = 4, CL = CL (IDD), AL = 0;
Operation Current
(Write)
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
IDD4W _{CKE is HIGH, CS is HIGH between valid commands;}
200
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
40
mA
18
70
mA
170
mA
160
mA
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2014
Revision : 1.0
6/59