M14D128168A Datasheet, PDF(20/59 Page) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

M14D128168A Datasheet, PDF (20/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

◁

ESMT

M14D128168A (2M)

Operation Temperature Condition (TC) -40Â°C~95Â°C

Slew Rate Definition Tangent

Elite Semiconductor Memory Technology Inc.

Publication Date : Feb. 2014

Revision : 1.0

20/59

▷