M14D128168A Datasheet, PDF (14/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D128168A (2M)
Operation Temperature Condition (TC) -40°C~95°C
column. {The less half-pulse width distortion present, the larger the t_QH value is; and the larger the valid data eye will be.}
Examples:
a. If the system provides t_HP of 1200 ps into a DDR2-800 SDRAM, the DRAM provides t_QH of 900 ps minimum.
b. If the system provides t_HP of 1300 ps into a DDR2-800 SDRAM, the DRAM provides t_QH of 1000 ps minimum.
8. RU stands for round up. WR refers to the t_WR parameter stored in the MRS.
9. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual t_ERR (6-10per) of the
input clock. (output de-ratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-800 SDRAM has t_ERR (6-10per)(min.) = - 272 ps and t_ERR (6-10per)(max.) =
+ 293 ps, then t_DQSCK (min.)(derated) = t_DQSCK (min.) - t_ERR (6-10per)(max.) = -350 ps - 293 ps = -643 ps and t_DQSCK (max.)
(derated) = t_DQSCK (max.) - t_ERR (6-10per)(min.) = 350 ps + 272 ps = +622 ps. Similarly, t_LZ (DQ) for DDR2-800 de-rates to
t_LZ (DQ)(min.)(derated) = -800 ps - 293 ps = -1093 ps and t_LZ (DQ)(max.)(derated) = 400 ps + 272 ps = +672 ps.
10. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual t_JIT (per) of the input
clock. (output de-ratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-800 SDRAM has t_JIT (per)(min.) = - 72 ps and t_JIT (per)(max.) = + 93 ps,
then t_RPRE (min.)(derated) = t_RPRE (min.) + t_JIT (per)(min.) = 0.9 x t_CK (avg) - 72 ps = + 2178 ps and t_RPRE (max.)(derated) =
t_RPRE (max.) + t_JIT (per)(max.) = 1.1 x t_CK (avg) + 93 ps = + 2843 ps.
11. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual t_JIT (duty) of the input
clock. (output de-ratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-800 SDRAM has t_JIT (duty)(min.) = - 72 ps and t_JIT (duty)(max.) = + 93 ps,
then t_RPST (min.)(derated) = t_RPST (min.) + t_JIT (duty)(min.) = 0.4 x t_CK (avg) - 72 ps = + 928 ps and t_RPST (max.)(derated) =
t_RPST (max.) + t_JIT (duty)(max.) = 0.6 x t_CK (avg) + 93 ps = + 1593 ps.
12. Refer to the Clock Jitter table.
13. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from t_AOND.
14. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from t_AOFD.
15. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual t_ERR (6-10per) of the
input clock. (output de-ratings are relative to the SDRAM input clock.)
16. When the device is operated with input clock jitter, this parameter needs to be derated by { - t_JIT (duty)(max.) - t_ERR
(6-10per)(max.) } and { - t_JIT (duty)(min.) - t_ERR (6-10per)(min.) } of the actual input clock. (output deratings are relative to
the SDRAM input clock.)
For example, if the measured jitter into a DDR2-800 SDRAM has t_ERR (6-10per)(min.) = - 272 ps, t_ERR (6- 10per)(max.) = +
293 ps, t_JIT (duty)(min.) = -96 ps and t_JIT (duty)(max.) = + 94 ps, then t_AOF(min.)(derated) = t_AOF(min.) + { - t_JIT (duty)(max.) -
t_ERR (6-10per)(max.) } = -400 ps + { - 94 ps - 293 ps} = -787 ps and t_AOF(max.)(derated) = t_AOF(max.) + { - t_JIT (duty)(min.) -
t_ERR (6-10per)(min.) } = 1000 ps + { 96 ps + 272 ps } = +1368 ps.
17. For t_AOFD of DDR2-800/1066, the 1/2 clock of t_CK in the 2.5 x t_CK assumes a t_CH (avg), average input clock HIGH pulse width
of 0.5 relative to t_CK (avg). t_AOF (min.) and t_AOF (max.) should each be derated by the same amount as the actual amount of
t_CH (avg) offset present at the DRAM input with respect to 0.5.
For example, if an input clock has a worst case t_CH (avg) of 0.48, the t_AOF (min.) should be derated by subtracting 0.02 x t_CK
(avg) from it, whereas if an input clock has a worst case t_CH (avg) of 0.52, the t_AOF (max.) should be derated by adding 0.02
x t_CK (avg) to it. Therefore, we have;
t_AOF (min.)(derated) = t_AC (min.) - [0.5 - Min(0.5, t_CH (avg)(min.))] x t_CK (avg)
t_AOF (max.)(derated) = t_AC (max.) + 0.6 + [Max(0.5, t_CH (avg)(max.)) - 0.5] x t_CK (avg)
or
t_AOF (min.)(derated) = Min(t_AC (min.), t_AC (min.) - [0.5 - t_CH (avg)(min.)] x t_CK (avg))
t_AOF (max.)(derated) = 0.6 + Max(t_AC (max.), t_AC (max.) + [t_CH (avg)(max.) - 0.5] x t_CK (avg)), where:
t_CH (avg)(min.) and t_CH (avg)(max.) are the minimum and maximum of t_CH (avg) actually measured at the DRAM input balls.
18. t_DAL [nCLK] = WR [nCLK] + tn_RP [nCLK] = WR + RU {t_RP [ps] / t_CK (avg) [ps] }, where WR is the value programmed in the
mode register set.
19. t_DAL = WR + RU{ t_RP[ns] / t_CK [ns] }, where RU stands for round up. WR refers to the t_WR parameter stored in the MRS. For
t_RP, if the result of the division is not already an integer, round up to the next highest integer. t_CK refers to the application
clock period.
Example: For DDR2-800 (5-5-5) at tCK =2.5ns with WR programmed to 6 clocks.
t_DAL = 6 + (12.5 ns / 2.5 ns) clocks = 6 + 5 clocks = 11 clocks.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2014
Revision : 1.0
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