M14D128168A Datasheet, PDF (11/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D128168A (2M)
Operation Temperature Condition (TC) -40°C~95°C
AC Timing Parameter & Specifications
Parameter
Symbol
-1.8
Min.
Max.
CL=7
1875
Clock period
CL=6
CL=5
t_CK (avg)
2500
3000
CL=4
3750
DQ output access time from
CLK/ CLK
t_AC
-350
CLK high-level width
CLK low-level width
DQS output access time from
CLK/ CLK
t_CH (avg)
t_CL (avg)
t_DQSCK
0.48
0.48
-325
Clock to first rising edge of DQS delay
Data-in and DM setup time (to DQS)
t_DQSS
t_DS
(base)
-0.25
0
Data-in and DM hold time (to DQS)
t_DH
(base)
75
DQ and DM input pulse width
(for each input)
t_DIPW
0.35
Address and Control Input setup time t_IS (base)
Address and Control Input hold time t_IH (base)
Control and Address input pulse width t_IPW
DQS input high pulse width
t_DQSH
DQS input low pulse width
t_DQSL
DQS falling edge to CLK rising setup
time
t_DSS
125
200
0.6
0.35
0.35
0.2
DQS falling edge from CLK rising hold
time
t_DSH
0.2
Data strobe edge to output data edge
Data-out high-impedance window from
CLK/ CLK
t_DQSQ
t_HZ
Data-out low-impedance window from tLZ
CLK/ CLK
(DQS)
t_AC(min.)
DQ low-impedance window from
CLK/ CLK
t_LZ
(DQ)
2 x t_AC(min.)
Half clock period
DQ/DQS output hold time from DQS
DQ hold skew factor
t_HP
t_QH
t_QHS
Min (t_CL, t_CH)
t_HP-t_QHS
7500
7500
7500
7500
+350
0.52
0.52
+325
+0.25
175
t_AC(max.)
t_AC(max.)
t_AC(max.)
250
-2.5
Min.
Max.
-
-
-
-
2500
3750
8000
8000
-400
+400
0.48
0.52
0.48
0.52
-350
+350
-0.25
50
+0.25
125
0.35
175
250
0.6
0.35
0.35
0.2
0.2
200
t_AC(max.)
t_AC(min.)
t_AC(max.)
2 x t_AC(min.) t_AC(max.)
Min (t_CL, t_CH)
t_HP-t_QHS
300
Unit Note
ps
12
ps
9
t_CK (avg) 12
t_CK (avg) 12
ps
9
t_CK (avg)
ps
3
ps
4
t_CK (avg)
ps
3
ps
4
t_CK (avg)
t_CK (avg)
t_CK (avg)
t_CK (avg)
t_CK (avg)
ps
ps
9
ps
9
ps
9
ps 5, 12
ps
ps
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2014
Revision : 1.0
11/59