M14D128168A Datasheet, PDF (31/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D128168A (2M)
Operation Temperature Condition (TC) -40°C~95°C
ODT Timing Mode Switch at Exiting Power-Down Mode
CLK
CLK
CKE
T0
T1
T4
T5
T6
T7
T8
T9
T10
T11
tAXPD
tIS
Exiting from slow Active Power-Down mode
or Precharge Power-Down mode.
Active and Standby
mode timings to
be applied.
ODT
Internal
Term Res.
Power-Down
mode timings to
be applied.
ODT
Internal
Term Res.
Active and Standby
mode timings to
be applied.
ODT
Internal
Term Res.
Power-Down
mode timings to
be applied.
ODT
Internal
Term Res.
tIS
tAOFD
Rtt
tIS
tAOFPD(max.)
Rtt
tIS
tAOND
Rtt
tIS
tAONPD(max.)
Rtt
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2014
Revision : 1.0
31/59