M14D128168A Datasheet, PDF (30/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D128168A (2M)
Operation Temperature Condition (TC) -40°C~95°C
ODT Timing Mode Switch at Entering Power-Down Mode
T-5
T-4
T-3
T-2
T-1
T0
T1
CLK
CLK
CKE
tANPD
tIS
Entering slow exit Active Power-Down mode
or Precharge Power-Down mode.
tIS
ODT
Internal
Term Res.
Rtt
tAOFD
ODT
Internal
Term Res.
tIS
tAOFPD(max.)
Rtt
ODT
Internal
Term Res.
ODT
Internal
Term Res.
tIS
tAOND
Rtt
tIS
tAONPD(max.)
Rtt
T2
T3
Active and Standby
mode timings to
be applied.
Power-Down
mode timings to
be applied.
Active and Standby
mode timings to
be applied.
Power-Down
mode timings to
be applied.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2014
Revision : 1.0
30/59