M14D128168A Datasheet, PDF (52/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D128168A (2M)
Operation Temperature Condition (TC) -40°C~95°C
Current State
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
CS RAS CAS WE
HXXX
L HHH
LHLH
L
H
L
L
L
L
H
H
L
L
H
L
L
L
L
H
L
L
L
L
HXXX
L HHH
LHLH
L
H
L
L
L
L
H
H
L
L
H
L
L
L
L
H
L
L
L
L
HXXX
L HHH
LHLX
PRE-CHARGIN
G
L
L
H
H
L
L
H
L
L
L
L
H
L
L
L
L
HXXX
L HHH
LHLX
ROW
ACTIVATING L
L
H
H
L
L
H
L
L
L
L
H
L
L
L
L
Address
Command
Action
X
DESEL
NOP (Continue Burst to end)
X
NOP
NOP (Continue Burst to end)
BA, CA, A10
READ / READA
ILLEGAL (*1)
BA, CA, A10
WRITE / WRITEA ILLEGAL (*1)
BA, RA
Active
ILLEGAL (*1)
BA, A10 / A10
PRE / PREA
ILLEGAL (*1) / ILLEGAL
X
Refresh
ILLEGAL
Op-Code Mode-Add MRS / EMRS
ILLEGAL
X
DESEL
NOP (Continue Burst to END)
X
NOP
NOP (Continue Burst to END)
BA, CA, A10
READ / READA
ILLEGAL (*1)
BA, CA, A10
WRITE / WRITEA ILLEGAL (*1)
BA, RA
Active
ILLEGAL (*1)
BA, A10
PRE / PREA
ILLEGAL (*1) / ILLEGAL
X
Refresh
ILLEGAL
Op-Code Mode-Add MRS / EMRS
ILLEGAL
X
X
BA, CA, A10
DESEL
NOP (Idle after t_RP)
NOP
NOP (Idle after t_RP)
READ / READA /
WRITE / WRITEA
ILLEGAL (*1)
BA, RA
Active
ILLEGAL (*1)
BA, A10 / A10
X
PRE / PREA
Refresh
NOP (Idle after t_RP)
ILLEGAL
Op-Code Mode-Add MRS / EMRS
ILLEGAL
X
X
BA, CA, A10
DESEL
NOP (Bank Active after t_RCD)
NOP
NOP (Bank Active after t_RCD)
READ / READA /
WRITE / WRITEA
ILLEGAL (*1, 5)
BA, RA
Active
ILLEGAL (*1)
BA, A10 / A10
PRE / PREA
ILLEGAL
X
Refresh
ILLEGAL
Op-Code Mode-Add MRS / EMRS
ILLEGAL
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2014
Revision : 1.0
52/59