M14D128168A Datasheet, PDF (29/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D128168A (2M)
Operation Temperature Condition (TC) -40°C~95°C
ODT Timing for Power-Down Mode
CLK
CLK
CKE
ODT
Internal
Term Res.
T0
T1
tIS
tAONPD(min.)
tAONPD(max.)
T2
T3
T4
tIS
tAOFPD(min.)
Rtt
T5
T6
tAOFPD(max.)
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2014
Revision : 1.0
29/59