M14D128168A Datasheet, PDF (13/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D128168A (2M)
Operation Temperature Condition (TC) -40°C~95°C
AC Timing Parameter & Specifications - Continued
Parameter
Output impedance test driver delay
MRS command to ODT update delay
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
ODT to Power-Down entry latency
ODT Power-Down exit latency
Symbol
-1.8
Min.
Max.
-2.5
Min.
Max.
t_OIT
t_MOD
t_AOND
t_AON
t_AONPD
0
12
0
12
0
12
0
12
2
2
2
2
t_AC(min.)
t_AC(max.)
+2.575
t_AC(min.) + 2
3 x t_CK (avg)
+t_AC(max.) + 1
t_AC(min.)
t_AC(min.) + 2
t_AC(max.) +0.7
2 x t_CK (avg)
+t_AC(max.) + 1
t_AOFD
2.5
2.5
2.5
2.5
t_AOF
t_AOFPD
t_ANPD
t_AXPD
t_AC(min.) t_AC(max.) +0.6
t_AC(min.) + 2
2.5 x t_CK (avg)
+t_AC(max.) + 1
4
t_AC(min.) t_AC(max.) +0.6
t_AC(min.) + 2
2.5 x t_CK (avg)
+t_AC(max.) + 1
3
11
8
Unit
ns
ns
t_CK
ns
ns
t_CK
ns
ns
t_CK
t_CK
Note
13,15
14,
16,17
Note:
1. AL: Additive Latency.
2. MRS A12 bit defines which Active Power-Down Exit timing to be applied.
3. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH (AC) level for a
rising signal and VIL (AC) for a falling signal applied to the device under test.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIL (DC) level for a rising
signal and VIH (DC) for a falling signal applied to the device under test.
5. t_HP is the minimum of the absolute half period of the actual input clock. t_HP is an input parameter but not an input
specification parameter. It is used in conjunction with t_QHS to derive the DRAM output timing t_QH. The value to be used for
t_QH calculation is determined by the following equation;
t_HP = Min ( t_CH (abs), t_CL (abs) ), where:
t_CH (abs) is the minimum of the actual instantaneous clock HIGH time;
t_CL (abs) is the minimum of the actual instantaneous clock LOW time;
6. t_QHS accounts for:
a. The pulse duration distortion of on-chip clock circuits, which represents how well the actual t_HP at the input is
transferred to the output; and
b. The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition,
both of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to
n-channel variation of the output drivers.
7. t_QH = t_HP - t_QHS, where:
t_HP is the minimum of the absolute half period of the actual input clock; and t_QHS is the specification value under the max
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2014
Revision : 1.0
13/59