EN27SN1G08 Datasheet, PDF (8/44 Pages) Eon Silicon Solution Inc. – 1 Gigabit (128 Mx 8), 1.8 V NAND Flash Memory

EN27SN1G08
Product Introduction
The device is a 1,056Mbit memory organized as 64K rows (pages) by 2,112x8 columns. Spare 64x8
columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to
memory cell arrays accommodating data transfer between the I/O buffers and memory during page read
and page program operations. The program and read operations are executed on a page basis, while
the erase operation is executed on a block basis. The memory array consists of 1,024 separately
erasable 128K-byte blocks. It indicates that the bit-by-bit erase operation is prohibited on the device.
The device has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and
allows system upgrades to future densities by maintaining consistency in system board design.
Command, address and data are all written through I/O's by bringing WE# to low while CE# is low.
Those are latched on the rising edge of WE#. Command Latch Enable (CLE) and Address Latch Enable
(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands
require one bus cycle. For example, Reset Command, Status Read Command, etc require just one
cycle bus. Some other commands, like page read and block erase and page program, require two
cycles: one cycle for setup and the other cycle for execution.
In addition to the enhanced architecture and interface, the device incorporates copy-back program
feature from one page to another page without need for transporting the data to and from the external
buffer memory.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21