EN27SN1G08 Datasheet, PDF (10/44 Pages) Eon Silicon Solution Inc. – 1 Gigabit (128 Mx 8), 1.8 V NAND Flash Memory

EN27SN1G08
DC AND OPERATION CHARACTERISTICS
(Recommended operating conditions otherwise noted)
Parameter
Symbol
Test Conditions
Min.
Typ.
Max. Unit
Operating
Page Read with
Serial Access
I_CC1
t_RC=45ns, CE# =V_IL, I_OUT=0mA
-
Current
Program
I_CC2
-
-
15
30
15
30
mA
Erase
I_CC3
-
-
15
30
Stand-by Current (TTL)
I_SB1
CE# =V_IH, WP# =0V/V_CC
-
-
1
mA
Stand-by Current (CMOS)
I_SB2
CE# = V_CC -0.2, WP# =0V/ V_CC
-
10
50
uA
Input Leakage Current
I_LI
V_IN=0 to V_CC (max)
-
-
±10
uA
Output Leakage Current
Input High Voltage
Input Low Voltage, All inputs
I_LO
V_IH ⁽¹⁾
V_IL ⁽¹⁾
V_OUT=0 to V_CC (max)
-
-
-
-
±10
uA
0.8 x V_CC
-
V_CC +0.3 V
-0.3
-
0.2 x V_CC V
Output High Voltage Level
V_OH
I_OH=-100uA
V_CC -0.1
-
-
V
Output Low Voltage Level
V_OL
I_OL=+100uA
-
-
0.1
V
Output Low Current (R/B#)
I_OL (R /B#) V_OL=0.1V
3
4
-
mA
Note:
1. V_IL can undershoot to -0.4V and V_IH can overshoot to V_CC+0.4V for durations of 20ns or less.
2. Typical value are measured at V_CC =1.8V, T_A = 25℃. And not 100% tested.
VALID BLOCK
Symbol
Min.
Typ.
Max.
Unit
N_VB
1,004
-
1,024
Blocks
Note:
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may
develop while being used. The number of valid blocks is presented as first shipped. Invalid blocks
are defined as blocks that contain one or more bad bits which cause status failure during program
and erase operation. Do not erase or program factory-marked bad blocks. Refer to the attached
technical notes for appropriate management of initial invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of
shipment and is guaranteed to be a valid block up to 1K program/erase cycles with 1 bit/528 bytes
ECC.
AC TEST CONDITION
(T_A = – 40°C to 85°C, V_CC=1.7V~1.95V)
Parameter
Condition
Input Pulse Levels
Input Rise and Fall Times
0V to V_CC
5 ns
Input and Output Timing Levels
Output Load
V_CC /2
1 TTL Gate and C_L=30pF
Note:
* Refer to Ready / Busy# section, R/B output’s Busy to Ready time is decided by the pull-up resistor (RP) tied to
R/B# pin.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21