EN27SN1G08 Datasheet, PDF(36/44 Page) Eon Silicon Solution Inc. – 1 Gigabit (128 Mx 8), 1.8 V NAND Flash Memory

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EN27SN1G08 Datasheet, PDF (36/44 Pages) Eon Silicon Solution Inc. – 1 Gigabit (128 Mx 8), 1.8 V NAND Flash Memory

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EN27SN1G08

Block Erase

The block-based Erase operation is initiated by an Erase Setup command (60h), followed by a two-cycle

row address, in which only Plane address and Block address are valid while Page address is ignored.

The Erase Confirm command (D0h) following the row address starts the internal erasing process. The

two-step command sequence is designed to prevent memory content from being inadvertently changed

by external noise. At the rising edge of WE# after the Erase Confirm command input, the internal

control logic handles erase and erase-verify. When the erase operation is completed, the host controller

can check Status bit (I/O0) to see if the erase operation is successfully done. The under figure illustrates

a block erase sequence, and the address input (the first page address of the selected block) is placed in

between commands 60h and D0h. After tBERASE erase time, the R/B# de-asserts to ready state. Read

Status command (70h) can be issued right after D0h to check the execution status of erase operation.

Block Erase Operation

Read Status

A status register on the device is used to check whether program or erase operation is completed and

whether the operation is completed successfully. After writing 70h command to the command register, a

read cycle outputs the content of the status register to I/O pins on the falling edge of CE or RE ,

whichever occurs last. These two commands allow the system to poll the progress of each device in

multiple memory connections even when R/B pins are common-wired. RE or CE does not need to

toggle for status change.

The command register remains in Read Status mode unless other commands are issued to it. Therefore,

if the status register is read during a random read cycle, a read command (00h) is needed to start read

cycles.

Status Register Definition for 70h Command

I/O

Page

Program

Block Erase

Read

Cache Read

Definition

I/O0

Pass / Fail

Pass: 0

Fail: 1

I/O1

Donât cared

I/O2

Donât cared

I/O3

Donât cared

I/O4

Donât cared

I/O5

Busy: 0

Ready / Busy True Ready / Busy

Ready: 1

I/O6 Ready / Busy Ready / Busy Ready / Busy

Ready / Busy

Busy: 0

Ready: 1

I/O7 Write Protect Write Protect Write Protect

Write Protect

Protected: 0

Not Protected: 1

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. B, Issue Date: 2012/05/21

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